Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654343
Jung Kyun Kim, Su-Heon Jeong
This paper shows that thermal characterization of TO-66 and TO-220 package transistors in avionics module using the thermal transient measurement method and simulation. To determine the thermal resistance values of the junction-to-case (RthJC), the JEDEC JESD 51-14 transient dual interface measurement method is a well-known and industry-wide accepted technique. In this article we also show a thermal model calibration tasks using transient thermal measurement. A detailed package model calibrated will allow even more accurate thermal simulations and improve the reliability of components.
{"title":"Thermal simulation and measurement of component in avionics","authors":"Jung Kyun Kim, Su-Heon Jeong","doi":"10.1109/EPTC.2018.8654343","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654343","url":null,"abstract":"This paper shows that thermal characterization of TO-66 and TO-220 package transistors in avionics module using the thermal transient measurement method and simulation. To determine the thermal resistance values of the junction-to-case (RthJC), the JEDEC JESD 51-14 transient dual interface measurement method is a well-known and industry-wide accepted technique. In this article we also show a thermal model calibration tasks using transient thermal measurement. A detailed package model calibrated will allow even more accurate thermal simulations and improve the reliability of components.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115279490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654368
Nan Wang, Yao Zhu, T. Lim, Navab Singh, Y. Gu
In this work, an aluminum nitride (AlN) based radiofrequency microelectromechanical system (RFMEMS) filter operating at 2.4GHz is characterized on a PCB through wirebonding connection, in order to study the effect of wirebonding on the performance of the filter, in particular the frequency response. Electrical characterization results show that the through proper impedance matching, the bonding wire has minimum effect on the passband and stopband response, e.g., bandwidth, insertion loss, and out-of-band rejection. However, the wirebonding introduces a spurious mode at around 2.37GHz. As a result, the roll-off of the lower edge of the passband gets disturbed. EM simulation will be done to better understand the response of the wirebonding and finally to eliminate the spurious mode.
{"title":"Effect of Wire Bonding on The Performance of RFMEMS Filters","authors":"Nan Wang, Yao Zhu, T. Lim, Navab Singh, Y. Gu","doi":"10.1109/EPTC.2018.8654368","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654368","url":null,"abstract":"In this work, an aluminum nitride (AlN) based radiofrequency microelectromechanical system (RFMEMS) filter operating at 2.4GHz is characterized on a PCB through wirebonding connection, in order to study the effect of wirebonding on the performance of the filter, in particular the frequency response. Electrical characterization results show that the through proper impedance matching, the bonding wire has minimum effect on the passband and stopband response, e.g., bandwidth, insertion loss, and out-of-band rejection. However, the wirebonding introduces a spurious mode at around 2.37GHz. As a result, the roll-off of the lower edge of the passband gets disturbed. EM simulation will be done to better understand the response of the wirebonding and finally to eliminate the spurious mode.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654351
G. Farkas, L. Gaal, A. Poppe, M. Rencz, R. Bornoff
The Industry 4.0 initiative targets the digitalization of design and manufacturing processes. The aim of the Delphi 4LED project of the EU is to trigger this transition in the solid-state lighting industry by developing testing and modeling methodologies aimed at multi-domain characterization of LED based products. In this paper we present the concept and describe our approaches in modeling to create the appropriate “digital twins” of LED packages, modules and luminaires to be used in virtual prototypes applied in different system level design tasks.
{"title":"LED multiphysics modeling for “Industry 4.0”, an approach proposed by the Delphi 4LED European project","authors":"G. Farkas, L. Gaal, A. Poppe, M. Rencz, R. Bornoff","doi":"10.1109/EPTC.2018.8654351","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654351","url":null,"abstract":"The Industry 4.0 initiative targets the digitalization of design and manufacturing processes. The aim of the Delphi 4LED project of the EU is to trigger this transition in the solid-state lighting industry by developing testing and modeling methodologies aimed at multi-domain characterization of LED based products. In this paper we present the concept and describe our approaches in modeling to create the appropriate “digital twins” of LED packages, modules and luminaires to be used in virtual prototypes applied in different system level design tasks.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654396
Qin Ren, W. Loh, Xiangy-Yu Wang
Through Silicon Via (TSV) is a high performance interconnect technique to enable 3D packaging. Compared to conventional 2D packaging using wire bonding or flip chip bonding, the length of the connections are shorter thus the interconnect and device density become higher. In this paper, we explored how combination of wet etch and Cu CMP can improve microscopic flatness for overburden removal after TSV Cu filling, while keeping the process cost low for Via-Last TSV fabrication.
{"title":"Development of cost effective Copper overburden removal for Via-Last TSV fabrication","authors":"Qin Ren, W. Loh, Xiangy-Yu Wang","doi":"10.1109/EPTC.2018.8654396","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654396","url":null,"abstract":"Through Silicon Via (TSV) is a high performance interconnect technique to enable 3D packaging. Compared to conventional 2D packaging using wire bonding or flip chip bonding, the length of the connections are shorter thus the interconnect and device density become higher. In this paper, we explored how combination of wet etch and Cu CMP can improve microscopic flatness for overburden removal after TSV Cu filling, while keeping the process cost low for Via-Last TSV fabrication.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654322
J. Son, S.G. Lee, Y. Lee, S. Jung
Mechanical property of Cu core solder ball (CCSB) was investigated with different plated SAC305 solder volume and thickness at the ball-grid-array (BGA) after reflow. Cu core ball size was $220mu m$ and plated SAC305 on Cu core ball was tested the 3 kinds of thickness such as $8mu m$, $18mu m$, $28mu m$ with $Nimu m$ on the Cu ball surface. The (Cu, Ni)6 Sn5 interfacial IMCs were formed at interface between Cu/Ni core ball and plated solder layer after reflow. In addition, (Cu, Ni)6 Sn5 IMC was also observed at interface between plated solder and Cu-OSP pad after reflow. And these interfacial IMCs were increased after multiple reflow. Additionally, thicker SAC plating layer has higher IMC growth rate than thinner plated CCSB. In the Cu core ball joint property, thicker SAC plated layer is, the higher ductile deformation length by ball shear test (BST). And thinner SAC plated CCSB showed larger reduction rate of ductile deformation length than thicker SAC plated CCSB at BST after multiple reflow. In SMT test, minimum plated solder volume and thickness was conformed and calculated to get the stable SMT yield after flip chip process. So, when targeting gap size between PKG and interposer and solder resist opening (SRO) size were designed for PoP PKG development, it is possible to calculation of Cu core ball size and needed minimum plated volume to get good workability yield at flip chip bonding process.
{"title":"Mechanical property and plated solder volume effect of Cu core ball","authors":"J. Son, S.G. Lee, Y. Lee, S. Jung","doi":"10.1109/EPTC.2018.8654322","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654322","url":null,"abstract":"Mechanical property of Cu core solder ball (CCSB) was investigated with different plated SAC305 solder volume and thickness at the ball-grid-array (BGA) after reflow. Cu core ball size was $220mu m$ and plated SAC305 on Cu core ball was tested the 3 kinds of thickness such as $8mu m$, $18mu m$, $28mu m$ with $Nimu m$ on the Cu ball surface. The (Cu, Ni)6 Sn5 interfacial IMCs were formed at interface between Cu/Ni core ball and plated solder layer after reflow. In addition, (Cu, Ni)6 Sn5 IMC was also observed at interface between plated solder and Cu-OSP pad after reflow. And these interfacial IMCs were increased after multiple reflow. Additionally, thicker SAC plating layer has higher IMC growth rate than thinner plated CCSB. In the Cu core ball joint property, thicker SAC plated layer is, the higher ductile deformation length by ball shear test (BST). And thinner SAC plated CCSB showed larger reduction rate of ductile deformation length than thicker SAC plated CCSB at BST after multiple reflow. In SMT test, minimum plated solder volume and thickness was conformed and calculated to get the stable SMT yield after flip chip process. So, when targeting gap size between PKG and interposer and solder resist opening (SRO) size were designed for PoP PKG development, it is possible to calculation of Cu core ball size and needed minimum plated volume to get good workability yield at flip chip bonding process.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115103399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654262
Ren-Fu Tsai, Pu-Hua Deng, Ting-Jung Chang
Conventional microstrip unequal Wilkinson power divider is difficult to be realized when the power ratio is not small because high impedance transmission line is usually used. Although the previous unequal divider in 2012 can relax the high impedance line usage, the structure results in low impedance line issue. Therefore, this study proposed a modified unequal Wilkinson power divider using T-shaped transformers can avoid high and low impedance lines simultaneously.
{"title":"A Modified Unequal Wilkinson Power Divider Using T-Shaped Transformers","authors":"Ren-Fu Tsai, Pu-Hua Deng, Ting-Jung Chang","doi":"10.1109/EPTC.2018.8654262","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654262","url":null,"abstract":"Conventional microstrip unequal Wilkinson power divider is difficult to be realized when the power ratio is not small because high impedance transmission line is usually used. Although the previous unequal divider in 2012 can relax the high impedance line usage, the structure results in low impedance line issue. Therefore, this study proposed a modified unequal Wilkinson power divider using T-shaped transformers can avoid high and low impedance lines simultaneously.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654275
Huimin He, Man Zhao, Fengman Liu, H. Xue, Yu Sun, Liqiang Cao
To realize high-bandwidth interconnection between the optical module and ASIC and to make the CPU maximize its performance, an optical transmission system which is equipped with 192channels running at 56Gbps/ch with PAM4 signals is designed and proposed in this article. In this transmission system, 4 optical transceivers and an ASIC chip are co-packaged in the ceramic substrate. The optical transceiver adopts the 2.5D packaging structure. To ensure the normal operation of the whole optical system, the electrical performance of the transmission are carefully evaluated and the advice to the layout of the optical chip is proposed. Besides, thermal management of the optical system is evaluated and optimized from the heat-dissipation structure. Ultimately, the temperature of all the chips in the optical system are controlled under 105□. After assessing the electrical and the thermal performance of the optical system, the packaging scheme is a potential method manner to reach the high-bandwidth and high-density interconnection.
{"title":"Design and optimization of the 10Tbps optical transmission system","authors":"Huimin He, Man Zhao, Fengman Liu, H. Xue, Yu Sun, Liqiang Cao","doi":"10.1109/EPTC.2018.8654275","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654275","url":null,"abstract":"To realize high-bandwidth interconnection between the optical module and ASIC and to make the CPU maximize its performance, an optical transmission system which is equipped with 192channels running at 56Gbps/ch with PAM4 signals is designed and proposed in this article. In this transmission system, 4 optical transceivers and an ASIC chip are co-packaged in the ceramic substrate. The optical transceiver adopts the 2.5D packaging structure. To ensure the normal operation of the whole optical system, the electrical performance of the transmission are carefully evaluated and the advice to the layout of the optical chip is proposed. Besides, thermal management of the optical system is evaluated and optimized from the heat-dissipation structure. Ultimately, the temperature of all the chips in the optical system are controlled under 105□. After assessing the electrical and the thermal performance of the optical system, the packaging scheme is a potential method manner to reach the high-bandwidth and high-density interconnection.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122010299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654304
K. Nishido, H. Onozeki, N. Suzuki, T. Nonaka
Die position accuracy is one of the important topics of the fabrication processes of die first fan out packages (FO-PKG). In this research, the die position accuracy and the compensation were studied by the combined approach of the sample preparation and the numerical calculation. As a result, the flow didn’t influence on the die shift significantly and the die shift could be estimated by the component material properties, which were the curing shrinkage of the EMC (epoxy molding compound), and the CTE (coefficient of thermal expansions) and the elastic moduli of the EMC, the TBA (temporary bonding adhesive) and the support. The value of the thermal die shift can be predicted by the developed formulasm. The pre-shift die mouting using the predicted value singnificanltly can suppress the thermal die shift.
{"title":"Study of the die position accuracy in the fabrication process of a die first type FO-PLP","authors":"K. Nishido, H. Onozeki, N. Suzuki, T. Nonaka","doi":"10.1109/EPTC.2018.8654304","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654304","url":null,"abstract":"Die position accuracy is one of the important topics of the fabrication processes of die first fan out packages (FO-PKG). In this research, the die position accuracy and the compensation were studied by the combined approach of the sample preparation and the numerical calculation. As a result, the flow didn’t influence on the die shift significantly and the die shift could be estimated by the component material properties, which were the curing shrinkage of the EMC (epoxy molding compound), and the CTE (coefficient of thermal expansions) and the elastic moduli of the EMC, the TBA (temporary bonding adhesive) and the support. The value of the thermal die shift can be predicted by the developed formulasm. The pre-shift die mouting using the predicted value singnificanltly can suppress the thermal die shift.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117097627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654291
H. Park, S. Kim
3D packaging technology offers great benefits such as reduced power consumption, improved performance, and reduced form factor. Among three key processes in 3D packaging a low temperature Cu-to-Cu wafer bonding is the subject of interest in this study. To accommodate high conductivity, non-formation of intermetallic compound, fine pitch connectivity, high pin count, and low cost, Cu-to-Cu wafer bonding is becoming increasingly important in advanced IC device packaging manufacturing. However, for high bonding quality, Cu-to-Cu wafer bonding requires high temperature process above $400^{circ}mathrm{C}$, which is not allowed in IC device packaging manufacturing. In this study the effect of Ar-N2 plasma treatment on Cu surface was investigated for low temperature Cu-to-Cu wafer bonding applications. Ar gas is used in a plasma ignition and the activation of Cu surface by ion bombardments, and the purpose of N2 gas was to passivate u surface from contaminations such as –O or –OH. The Cu/Ti/SiO2/Si specimens were fabricated on 8-inch Si wafers. Then various Ar-N2 plasma treatments were performed on Cu wafer surface. After the Ar-N2 plasma treatments, electrical and structural properties were analyzed by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscope, and 4-point probe measurements. It has been confirmed that Ar-N2 plasma treatment can provide copper oxide removal and copper nitride passivation at the topmost Cu surface.
{"title":"Effect of Ar-N2Plasma Treatment on Copper Surface for Cu-to-Cu Wafer Bonding","authors":"H. Park, S. Kim","doi":"10.1109/EPTC.2018.8654291","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654291","url":null,"abstract":"3D packaging technology offers great benefits such as reduced power consumption, improved performance, and reduced form factor. Among three key processes in 3D packaging a low temperature Cu-to-Cu wafer bonding is the subject of interest in this study. To accommodate high conductivity, non-formation of intermetallic compound, fine pitch connectivity, high pin count, and low cost, Cu-to-Cu wafer bonding is becoming increasingly important in advanced IC device packaging manufacturing. However, for high bonding quality, Cu-to-Cu wafer bonding requires high temperature process above $400^{circ}mathrm{C}$, which is not allowed in IC device packaging manufacturing. In this study the effect of Ar-N2 plasma treatment on Cu surface was investigated for low temperature Cu-to-Cu wafer bonding applications. Ar gas is used in a plasma ignition and the activation of Cu surface by ion bombardments, and the purpose of N2 gas was to passivate u surface from contaminations such as –O or –OH. The Cu/Ti/SiO2/Si specimens were fabricated on 8-inch Si wafers. Then various Ar-N2 plasma treatments were performed on Cu wafer surface. After the Ar-N2 plasma treatments, electrical and structural properties were analyzed by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscope, and 4-point probe measurements. It has been confirmed that Ar-N2 plasma treatment can provide copper oxide removal and copper nitride passivation at the topmost Cu surface.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129016713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654354
L. W. Lee, M. Stefenelli, Agala Joel Baldevia, N. Evelyn
An electro assisted advanced adhesion promoter process is used to increase the mechanical and chemical robustness between mold compound and metal areas in the package [1], [2]. As quality monitoring method optical inspection is used. Where, for one product, a significant color difference between bond pads within a chip was observed. Our investigations proved that the color differences after the plating process are mainly due to the electrical characteristic of the specific chip in the specific product leading to electronegative static charge on individual bond pads.
{"title":"Understanding of within Chip variation of optical appearance of Aluminum Pads","authors":"L. W. Lee, M. Stefenelli, Agala Joel Baldevia, N. Evelyn","doi":"10.1109/EPTC.2018.8654354","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654354","url":null,"abstract":"An electro assisted advanced adhesion promoter process is used to increase the mechanical and chemical robustness between mold compound and metal areas in the package [1], [2]. As quality monitoring method optical inspection is used. Where, for one product, a significant color difference between bond pads within a chip was observed. Our investigations proved that the color differences after the plating process are mainly due to the electrical characteristic of the specific chip in the specific product leading to electronegative static charge on individual bond pads.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129464792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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