S. Huss, M. Mullen, C. T. Gray, Randall Smith, M. Summers, J. Shafer, Pat Heron, Tim Sawinska, Joe Medero
{"title":"A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 /spl mu/m CMOS technology","authors":"S. Huss, M. Mullen, C. T. Gray, Randall Smith, M. Summers, J. Shafer, Pat Heron, Tim Sawinska, Joe Medero","doi":"10.1109/CICC.2001.929741","DOIUrl":null,"url":null,"abstract":"This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 /spl mu/m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm/sup 2/ and consumes 350 mW of power.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929741","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 /spl mu/m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm/sup 2/ and consumes 350 mW of power.
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