{"title":"A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement","authors":"Eunseon Yu, Seongjae Cho","doi":"10.1109/SISPAD.2018.8551621","DOIUrl":null,"url":null,"abstract":"In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2018.8551621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.