Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551710
M. Duan, B. Cheng, F. Adamu-Lema, P. Asenov, T. Dutta, X. Wang, V. Georgiev, C. Millar, P. Pfaeffli, A. Asenov
The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2–5] has been demonstrated as a promising DRAM candidate eliminating theneed for external capacitor. In the past, attention was focused on the optimization of device structure [5] and fabrication process [2] without paying much attention to the Statistical (local) Variability (SV) which is crucial for any memory technology. In this paper, a novel simulation methodology is proposed and the SV of DRAM Memory Window (MW) is investigated systematically. It is found that SV of MW is dominated by Metal Gate Granularity (MGG) coming from the Gated-SOI region of the Z2FET. Although Random Discrete Dopant (RDD) induced variations in the threshold voltage (Vth) has larger spread in the Intrinsic-SOI part, it has no significant effect on the overall Z2FET characteristics. Based on the proposed methodology, SV of MW at different process corners has also been studied. Results reveal the necessity for further process optimization due to the best corner giving rise not only to larger average MW but also less variations. Furthermore, circuit level read performance (including the variability) of a Z2FET-based memory cell have been evaluated. All these findings could guide the further performance optimization from both device and memory cell circuit point of view for Z2FET-based volatile memory product development.
{"title":"Statistical Variability Simulation of Novel Capacitor-less Z2FET DRAM: From Transistor to}Circuit","authors":"M. Duan, B. Cheng, F. Adamu-Lema, P. Asenov, T. Dutta, X. Wang, V. Georgiev, C. Millar, P. Pfaeffli, A. Asenov","doi":"10.1109/SISPAD.2018.8551710","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551710","url":null,"abstract":"The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2–5] has been demonstrated as a promising DRAM candidate eliminating theneed for external capacitor. In the past, attention was focused on the optimization of device structure [5] and fabrication process [2] without paying much attention to the Statistical (local) Variability (SV) which is crucial for any memory technology. In this paper, a novel simulation methodology is proposed and the SV of DRAM Memory Window (MW) is investigated systematically. It is found that SV of MW is dominated by Metal Gate Granularity (MGG) coming from the Gated-SOI region of the Z2FET. Although Random Discrete Dopant (RDD) induced variations in the threshold voltage (Vth) has larger spread in the Intrinsic-SOI part, it has no significant effect on the overall Z2FET characteristics. Based on the proposed methodology, SV of MW at different process corners has also been studied. Results reveal the necessity for further process optimization due to the best corner giving rise not only to larger average MW but also less variations. Furthermore, circuit level read performance (including the variability) of a Z2FET-based memory cell have been evaluated. All these findings could guide the further performance optimization from both device and memory cell circuit point of view for Z2FET-based volatile memory product development.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115116923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551620
Andy Huang, Xujiao Gao, R. Pawlowski, J. Gates, L. Musson, G. Hennigan, Mihai Negoita
In this paper, we present a parallelized and versatile harmonic balance approach for modeling the small-signal and large-signal frequency-domain response of the coupled semiconductor drift-diffusion equations used in TCAD device simulations. Our approach begins with a time-domain TCAD code, and we describe the process to adapt the system into the frequency domain so that the transformation can be parallelized. Both small-signal and large-signal analyses are easily simultaneously incorporated. Furthermore, we introduce the Isofrequency Remapping Scheme, so that an arbitrary number of high frequencies can be analyzed without introducing a prohibitive expense. Results obtained by our small-signal and large signal harmonic balance methods are shown to capture the same response for a linear device, as expected. Further results use our harmonic balance method to explore a prohibitively expensive time-domain problem: a large-signal, two-tone simulation too costly for a time-domain analysis, for which we are able to produce the expected response with intermodulation.
{"title":"A versatile harmonic balance method in a parallel framework","authors":"Andy Huang, Xujiao Gao, R. Pawlowski, J. Gates, L. Musson, G. Hennigan, Mihai Negoita","doi":"10.1109/SISPAD.2018.8551620","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551620","url":null,"abstract":"In this paper, we present a parallelized and versatile harmonic balance approach for modeling the small-signal and large-signal frequency-domain response of the coupled semiconductor drift-diffusion equations used in TCAD device simulations. Our approach begins with a time-domain TCAD code, and we describe the process to adapt the system into the frequency domain so that the transformation can be parallelized. Both small-signal and large-signal analyses are easily simultaneously incorporated. Furthermore, we introduce the Isofrequency Remapping Scheme, so that an arbitrary number of high frequencies can be analyzed without introducing a prohibitive expense. Results obtained by our small-signal and large signal harmonic balance methods are shown to capture the same response for a linear device, as expected. Further results use our harmonic balance method to explore a prohibitively expensive time-domain problem: a large-signal, two-tone simulation too costly for a time-domain analysis, for which we are able to produce the expected response with intermodulation.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551731
Shang-Chun Lu, Yuanchen Chu, Youngseok Kim, M. Mohamed, Gerhard Klimeck, T. Palacios, Umberto Ravaioli
New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and Ion/Ioff > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.
{"title":"Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications","authors":"Shang-Chun Lu, Yuanchen Chu, Youngseok Kim, M. Mohamed, Gerhard Klimeck, T. Palacios, Umberto Ravaioli","doi":"10.1109/SISPAD.2018.8551731","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551731","url":null,"abstract":"New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and Ion/Ioff > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551656
Venkata Pavan Kumar Miriyala
Though physical mechanisms such as spin-transfer torque (STT), spin-orbit torque (SOT), and voltage-controlled magnetic anisotropy (VCMA) has potential to enable energyefficient and ultra-fast switching of spintronic devices, the switching dynamics are stochastic due to thermal fluctuations. Thus, there is a need in spintronics to understand the interactions between circuit design and the error rate in the switching mechanism, called as write error rate. In this paper, we propose a novel devices-to-circuits simulation framework (FANTASI) for fast estimation of the write error rates (WER) in different spintronic devices and circuits. Here, we show that, FANTASI enables efficient spintronic device-circuit co-design, with results in good agreement with the experimental measurements.
{"title":"FANTASI: A novel devices-to-circuits simulation framework for fast estimation of write error rates in spintronics","authors":"Venkata Pavan Kumar Miriyala","doi":"10.1109/SISPAD.2018.8551656","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551656","url":null,"abstract":"Though physical mechanisms such as spin-transfer torque (STT), spin-orbit torque (SOT), and voltage-controlled magnetic anisotropy (VCMA) has potential to enable energyefficient and ultra-fast switching of spintronic devices, the switching dynamics are stochastic due to thermal fluctuations. Thus, there is a need in spintronics to understand the interactions between circuit design and the error rate in the switching mechanism, called as write error rate. In this paper, we propose a novel devices-to-circuits simulation framework (FANTASI) for fast estimation of the write error rates (WER) in different spintronic devices and circuits. Here, we show that, FANTASI enables efficient spintronic device-circuit co-design, with results in good agreement with the experimental measurements.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/sispad.2018.8551726
{"title":"SISPAD 2018 Conference Schedule at a Glance","authors":"","doi":"10.1109/sispad.2018.8551726","DOIUrl":"https://doi.org/10.1109/sispad.2018.8551726","url":null,"abstract":"","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124606471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551708
O. Olanrewaju, A. Castellazzi
This work proposes the development of a simplified thermo-mechanical model suitable for coupling with device physics and a 3D electrothermal model in line with the creation of a comprehensive framework for circuit simulation of multidomain problems. Commercially available numerical analysis software are capable of showing thermo-mechanical effects but lack real-time feedback between domains and require sophisticated CAD/meshing. Here, we show a ID mechanical model coupled to a thermal model which is capable of generating accurate mechanical Strain and stress values of a power assembly while optimizing the tradeoff with computational efficiency. The thermo-mechanical model was created in VHDL-AMS language because of the multi-domain capability of VHDL-AMS.
{"title":"VHDL-AMS Thermo-Mechanical Model for Coupled Analysis of Power Module Degradation in Circuit Simulation Environments","authors":"O. Olanrewaju, A. Castellazzi","doi":"10.1109/SISPAD.2018.8551708","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551708","url":null,"abstract":"This work proposes the development of a simplified thermo-mechanical model suitable for coupling with device physics and a 3D electrothermal model in line with the creation of a comprehensive framework for circuit simulation of multidomain problems. Commercially available numerical analysis software are capable of showing thermo-mechanical effects but lack real-time feedback between domains and require sophisticated CAD/meshing. Here, we show a ID mechanical model coupled to a thermal model which is capable of generating accurate mechanical Strain and stress values of a power assembly while optimizing the tradeoff with computational efficiency. The thermo-mechanical model was created in VHDL-AMS language because of the multi-domain capability of VHDL-AMS.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122013318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551666
Yuanchen Chu, Prasad Sarangapani, J. Charles, Gerhard Klimeck, T. Kubis
State of the art quantum transport models for semi-conductor nanodevices attribute negative (positive) unit charges to states of the conduction (valence) band. Hybrid states that enable band-to-band tunneling are subject to interpolation that yield model dependent charge contributions. In any nanodevice structure, these models rely on device and physics specific input for the dielectric constants. This work exemplifies the large variability of different charge interpretation models when applied to ultrathin body transistor performance predictions. To solve this modeling challenge, an electron-only band structure model is extended to atomistic quantum transport. Performance predictions of MOSFETs and tunneling FETs confirm the generality of the new model and its independence of additional screening models.
{"title":"Electron-only explicit screening quantum transport model for semiconductor nanodevices","authors":"Yuanchen Chu, Prasad Sarangapani, J. Charles, Gerhard Klimeck, T. Kubis","doi":"10.1109/SISPAD.2018.8551666","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551666","url":null,"abstract":"State of the art quantum transport models for semi-conductor nanodevices attribute negative (positive) unit charges to states of the conduction (valence) band. Hybrid states that enable band-to-band tunneling are subject to interpolation that yield model dependent charge contributions. In any nanodevice structure, these models rely on device and physics specific input for the dielectric constants. This work exemplifies the large variability of different charge interpretation models when applied to ultrathin body transistor performance predictions. To solve this modeling challenge, an electron-only band structure model is extended to atomistic quantum transport. Performance predictions of MOSFETs and tunneling FETs confirm the generality of the new model and its independence of additional screening models.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551695
Moon-Deock Kim, Junbeom Seo, M. Shin
In this work, we report device simulations conducted to study the performance of biaxially strained ferroelectric-based negative capacitance FETs (NCFETs). We adopted PbZr0.5 Ti0.5 O3 (PZT) and HfO2 as ferroelectric materials and applied biaxial strain using the first-principles method. It was found that PZT and HfO2 show different trends in the negative capacitance (NC) region under biaxial strain. Biaxial strain strongly affects the NC of PZT, whereas HfO2 is not as susceptible to biaxial strain as PZT. When no strain is applied, HfO2-based NCFETs exhibit a better performance than PZT-based NCFETs. However, the subthreshold slope and ON-state current are improved in the case of PZT-based NCFETs when the compressive biaxial strain is increased, whereas the performance of HfO2 based NCFETs is slightly degraded. In particular, the negative drain-induced barrier lowering and negative differential resistance vary considerably when compressive strain is applied to PZT-based NCFETs.
{"title":"Biaxial Strain based Performance Modulation of Negative-Capacitance FETs","authors":"Moon-Deock Kim, Junbeom Seo, M. Shin","doi":"10.1109/SISPAD.2018.8551695","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551695","url":null,"abstract":"In this work, we report device simulations conducted to study the performance of biaxially strained ferroelectric-based negative capacitance FETs (NCFETs). We adopted PbZr0.5 Ti0.5 O3 (PZT) and HfO2 as ferroelectric materials and applied biaxial strain using the first-principles method. It was found that PZT and HfO2 show different trends in the negative capacitance (NC) region under biaxial strain. Biaxial strain strongly affects the NC of PZT, whereas HfO2 is not as susceptible to biaxial strain as PZT. When no strain is applied, HfO2-based NCFETs exhibit a better performance than PZT-based NCFETs. However, the subthreshold slope and ON-state current are improved in the case of PZT-based NCFETs when the compressive biaxial strain is increased, whereas the performance of HfO2 based NCFETs is slightly degraded. In particular, the negative drain-induced barrier lowering and negative differential resistance vary considerably when compressive strain is applied to PZT-based NCFETs.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120810076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551672
Ken Suzuki, Fang Yiqing, Yifan Luo, H. Miura
In this study, grain boundary quality in terms of order of atomic arrangement of electroplated copper thin films was evaluated by using the IQ (Image Quality) value obtained from an electron back-scatter diffraction (EBSD) method, and the grain and grain boundary strength was evaluated by applying micro tensile test. In addition, in order to investigate the relationship between the strength and grain boundary quality, molecular dynamics (MD) simulations were applied to analyze the deformation behavior of a bicrystal sample and its strength. The variation of the strength and deformation property were attributed to the higher defect density around grain boundaries than that in grains, which impeded the development of slip systems.
{"title":"Effect of Defects on the Grain and Grain Boundary Strength in Polycrystalline Copper Thin Films","authors":"Ken Suzuki, Fang Yiqing, Yifan Luo, H. Miura","doi":"10.1109/SISPAD.2018.8551672","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551672","url":null,"abstract":"In this study, grain boundary quality in terms of order of atomic arrangement of electroplated copper thin films was evaluated by using the IQ (Image Quality) value obtained from an electron back-scatter diffraction (EBSD) method, and the grain and grain boundary strength was evaluated by applying micro tensile test. In addition, in order to investigate the relationship between the strength and grain boundary quality, molecular dynamics (MD) simulations were applied to analyze the deformation behavior of a bicrystal sample and its strength. The variation of the strength and deformation property were attributed to the higher defect density around grain boundaries than that in grains, which impeded the development of slip systems.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551729
Pratik B. Vyas, M. L. Van de Put, M. Fischetti
Quantum simulation of electronic transport in double gate (DG) field-effect transistors (FETs) and FinFETs is usually deemed to be required as the devices are scaled to the nanometer length-scale. Here, we present results obtained using a simulation program to model ballistic quantum transport in these devices. Our quantum simulations show the presence of quasi bound electronic states in the channel and Fano-interference phenomenon in the transport behavior of ultra-thin body (UTB) Si DG MOSFETs. Vortices in electron wavefunctions are also reported at energies at which transmission zeros (antiresonance) occur.
双栅极场效应晶体管(fet)和finfet中电子输运的量子模拟通常被认为是器件缩放到纳米长度尺度的必要条件。在这里，我们展示了使用模拟程序来模拟这些器件中的弹道量子输运的结果。我们的量子模拟显示了超薄体(UTB) Si DG mosfet的通道中存在准束缚电子态和输运行为中的fano干扰现象。电子波函数中的涡旋也在传输零点(反共振)发生的能量处被报道。
{"title":"Simulation of Quantum Current in Double Gate MOSFETs: Vortices in Electron Transport","authors":"Pratik B. Vyas, M. L. Van de Put, M. Fischetti","doi":"10.1109/SISPAD.2018.8551729","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551729","url":null,"abstract":"Quantum simulation of electronic transport in double gate (DG) field-effect transistors (FETs) and FinFETs is usually deemed to be required as the devices are scaled to the nanometer length-scale. Here, we present results obtained using a simulation program to model ballistic quantum transport in these devices. Our quantum simulations show the presence of quasi bound electronic states in the channel and Fano-interference phenomenon in the transport behavior of ultra-thin body (UTB) Si DG MOSFETs. Vortices in electron wavefunctions are also reported at energies at which transmission zeros (antiresonance) occur.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128484565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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