{"title":"Patil array-a Petri net hardware implementation","authors":"R. Hartenstein, A. Hirschbiel, M. Weber","doi":"10.1109/CMPEUR.1988.4931","DOIUrl":null,"url":null,"abstract":"The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPEUR.1988.4931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
![[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools](/Content/css/sci/img/zetp.jpg)
求助内容：
应助结果提醒方式：
扫码关注我们
