Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4967
J. Katzenelson, R. Zippel
It is argued that systems should be designed for reusability by anticipating change. This goal can be achieved by designing the software by layers of problem-oriented languages, which are implemented by suitably extending a base language. A language layer rarely needs to be adapted to changes, only the application (i.e. algorithm) has to be changed. The authors illustrate this methodology with respect to VLSI CAD programs and a particular language layer: a language for handling networks. Such a language consists of a base language (EC or Lisp) plus data types, operations and control structures that are relevant to network problems. The network language is but one of several languages used; other languages used deal with sets, two-dimensional layout structures, waveforms, etc. The discussion of the network language illustrates this technique.<>
{"title":"Software structuring principles for VLSI CAD","authors":"J. Katzenelson, R. Zippel","doi":"10.1109/CMPEUR.1988.4967","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4967","url":null,"abstract":"It is argued that systems should be designed for reusability by anticipating change. This goal can be achieved by designing the software by layers of problem-oriented languages, which are implemented by suitably extending a base language. A language layer rarely needs to be adapted to changes, only the application (i.e. algorithm) has to be changed. The authors illustrate this methodology with respect to VLSI CAD programs and a particular language layer: a language for handling networks. Such a language consists of a base language (EC or Lisp) plus data types, operations and control structures that are relevant to network problems. The network language is but one of several languages used; other languages used deal with sets, two-dimensional layout structures, waveforms, etc. The discussion of the network language illustrates this technique.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128252593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4948
F. Hoppe
The author presents a modified time-warp algorithm for parallel logic simulation using circuit partitioning. The algorithm allows a processor to roll back its simulation time to any given point in the past, only using the input queue. The memory space for the state queue and the output queue and the computing effort to handle them can be saved. A software model of a distributed system has been developed as test environment for the implementation of the modified algorithm, which is compared with the link time algorithm and with a sequential simulation. It is shown that the speedup of the time-warp method is less dependent on cycles in the communication graph (feedbacks in the test-circuit) than the link time method.<>
{"title":"Accelerated logic simulation using parallel processing","authors":"F. Hoppe","doi":"10.1109/CMPEUR.1988.4948","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4948","url":null,"abstract":"The author presents a modified time-warp algorithm for parallel logic simulation using circuit partitioning. The algorithm allows a processor to roll back its simulation time to any given point in the past, only using the input queue. The memory space for the state queue and the output queue and the computing effort to handle them can be saved. A software model of a distributed system has been developed as test environment for the implementation of the modified algorithm, which is compared with the link time algorithm and with a sequential simulation. It is shown that the speedup of the time-warp method is less dependent on cycles in the communication graph (feedbacks in the test-circuit) than the link time method.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4962
M. Wirsing
An approach to the description of reusable software components is presented which is based on the algebraic specification of abstract data types. Reusable components are described by an extension of the specification language ASL, which contains features for hierarchical structuring, parameterization, encapsulation of components, extension by enrichment, export-import interfaces, abstraction from the observable behavior, and the combination of components. Simple examples of ASL specifications are given, a notion of implementation is presented, and a few transformations of specifications are shown. A reusable component consists of tree formal specifications where a specification is a child of another specification if it is an implementation. Every node of the tree is itself a structured specification. In contrast to other approaches to software reusability these trees are considered as objects of the language and can be constructed and manipulated by operators of the language.<>
{"title":"Algebraic description of reusable software components","authors":"M. Wirsing","doi":"10.1109/CMPEUR.1988.4962","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4962","url":null,"abstract":"An approach to the description of reusable software components is presented which is based on the algebraic specification of abstract data types. Reusable components are described by an extension of the specification language ASL, which contains features for hierarchical structuring, parameterization, encapsulation of components, extension by enrichment, export-import interfaces, abstraction from the observable behavior, and the combination of components. Simple examples of ASL specifications are given, a notion of implementation is presented, and a few transformations of specifications are shown. A reusable component consists of tree formal specifications where a specification is a child of another specification if it is an implementation. Every node of the tree is itself a structured specification. In contrast to other approaches to software reusability these trees are considered as objects of the language and can be constructed and manipulated by operators of the language.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4933
E. Shragowitz, H. Youssef, L. Bening
A major problem in hierarchical design is to achieve consistency of the design steps that will not require iterations and will converge to the 'reasonably good' solution. To achieve this goal, additional efforts need to be made of each level of the hierarchical top-down process to derive constraints on variables of the lower level of hierarchy and use these additional constraints to solve the problems of lower levels. The authors illustrate this concept with the design step positioned between the logical level of simulation for VLSI and the physical implementation of the design. This step performs the timing analysis of the logic and provides constraints for the physical implementation of the design. If these constraints are satisfied on the layout phase, then timing-error-free design is obtained.<>
{"title":"Predictive tools in VLSI system design: timing aspects","authors":"E. Shragowitz, H. Youssef, L. Bening","doi":"10.1109/CMPEUR.1988.4933","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4933","url":null,"abstract":"A major problem in hierarchical design is to achieve consistency of the design steps that will not require iterations and will converge to the 'reasonably good' solution. To achieve this goal, additional efforts need to be made of each level of the hierarchical top-down process to derive constraints on variables of the lower level of hierarchy and use these additional constraints to solve the problems of lower levels. The authors illustrate this concept with the design step positioned between the logical level of simulation for VLSI and the physical implementation of the design. This step performs the timing analysis of the logic and provides constraints for the physical implementation of the design. If these constraints are satisfied on the layout phase, then timing-error-free design is obtained.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121708243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4947
Y. Shiran
A description is given of a database representation of VLSI circuits and the algorithms used to build and access it. Since the database is used in the layout verification process, it is being built from a flat (SPICE2-type) description of the circuit which is extracted from the layout masks. Other databases are built during the engineering process and usually rely on the hierarchy of the chip for partitioning purposes. The capability of partitioning a flat description and building a database from such a representation is the novel idea presented. The partitioning is performed by a graph algorithm which is superior to other algorithms in that it is technology-independent. A database organization is presented that achieves fast navigation capability by using architectural access methods such as rooms, floors, stairs, corridors, and hallways. The computational complexity of the partitioning algorithm, as well as the access time for a single device, is linear with the average number of devices connected to a single net. The database is used commercially as part of the YNCC network comparison program. Circuits in the 200 K-component range are considered.<>
{"title":"YNCC/sub DB/: a new database representation of VLSI circuits for fast navigation and layout verification applications","authors":"Y. Shiran","doi":"10.1109/CMPEUR.1988.4947","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4947","url":null,"abstract":"A description is given of a database representation of VLSI circuits and the algorithms used to build and access it. Since the database is used in the layout verification process, it is being built from a flat (SPICE2-type) description of the circuit which is extracted from the layout masks. Other databases are built during the engineering process and usually rely on the hierarchy of the chip for partitioning purposes. The capability of partitioning a flat description and building a database from such a representation is the novel idea presented. The partitioning is performed by a graph algorithm which is superior to other algorithms in that it is technology-independent. A database organization is presented that achieves fast navigation capability by using architectural access methods such as rooms, floors, stairs, corridors, and hallways. The computational complexity of the partitioning algorithm, as well as the access time for a single device, is linear with the average number of devices connected to a single net. The database is used commercially as part of the YNCC network comparison program. Circuits in the 200 K-component range are considered.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124277264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4934
B. Kaminska, Y. Savaria, J. Houle
A framework is presented for the prediction and estimation of the design yield of VLSI systems through design refinement steps. The design yield is calculated from simple analytical formulas and provides an effective early-warning tool for the logic designer that can be used to eliminate the necessity of running simulation programs for different versions of a given design. A number of metrics that are useful during the design process are introduced. These metrics can be included into a set of CAD tools. Test cost minimization is proposed as a possible application of this approach. Finally, a small example is developed to demonstrate that this approach is practical.<>
{"title":"Design model on performance prediction for VLSI systems","authors":"B. Kaminska, Y. Savaria, J. Houle","doi":"10.1109/CMPEUR.1988.4934","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4934","url":null,"abstract":"A framework is presented for the prediction and estimation of the design yield of VLSI systems through design refinement steps. The design yield is calculated from simple analytical formulas and provides an effective early-warning tool for the logic designer that can be used to eliminate the necessity of running simulation programs for different versions of a given design. A number of metrics that are useful during the design process are introduced. These metrics can be included into a set of CAD tools. Test cost minimization is proposed as a possible application of this approach. Finally, a small example is developed to demonstrate that this approach is practical.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":" 630","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120827512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4945
H. Sharp, C. Easteal
The idea of an automated support tool for evaluating and refining a design, based on the blackboard model of control, is introduced. An implementation of such a tool, based on structural techniques, is presented. The tool's architecture and an example session are included and explained.<>
{"title":"Automatic design evaluation and refinement using the blackboard model of control","authors":"H. Sharp, C. Easteal","doi":"10.1109/CMPEUR.1988.4945","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4945","url":null,"abstract":"The idea of an automated support tool for evaluating and refining a design, based on the blackboard model of control, is introduced. An implementation of such a tool, based on structural techniques, is presented. The tool's architecture and an example session are included and explained.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"89 35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129795944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4950
M. Jarke
Decision support systems (DSS) combine methods of business administration, mathematics, databases, and dialog systems to assist responsibles in modelling and resolving complex decision problems. DSS are usually configured from existing, often mathematical, representations and tools for the chosen application domain. The traditional difficulty that models are either oversimplified or rejected by decisionmakers for incomprehensibility can be, overcome in part, by attaching knowledge-based control mechanisms. The author presents language concepts and example systems that realize this coupling approach, and sketches a concept for integrated, normatively oriented DSS modeling and solution environments based on the idea of model reusability.<>
{"title":"Coupling conceptual and numerical models in decision support","authors":"M. Jarke","doi":"10.1109/CMPEUR.1988.4950","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4950","url":null,"abstract":"Decision support systems (DSS) combine methods of business administration, mathematics, databases, and dialog systems to assist responsibles in modelling and resolving complex decision problems. DSS are usually configured from existing, often mathematical, representations and tools for the chosen application domain. The traditional difficulty that models are either oversimplified or rejected by decisionmakers for incomprehensibility can be, overcome in part, by attaching knowledge-based control mechanisms. The author presents language concepts and example systems that realize this coupling approach, and sketches a concept for integrated, normatively oriented DSS modeling and solution environments based on the idea of model reusability.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4952
P. Baanen
The author presents a built-in self test method for word-oriented embedded static RAMs. Based on bit-oriented march tests, which are very suitable for self-test applications, word-oriented extensions are presented and analyzed for fault coverage. The self-test algorithm gives a high fault coverage for digital faults. Besides simple stuck-at faults, it detects transition faults and multiple-access faults. Also, all two-coupling faults between arbitrary pairs of cells are detected, so no knowledge of the physical placement of the cells is required. A prototype of the hardware implementation of the BIST method shows that the overhead, especially for large RAMs, is quite modest. The self-test hardware can be parameterized to size, making automatic generation by a module compiler easy.<>
{"title":"Testing word oriented embedded RAMs using built-in self test","authors":"P. Baanen","doi":"10.1109/CMPEUR.1988.4952","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4952","url":null,"abstract":"The author presents a built-in self test method for word-oriented embedded static RAMs. Based on bit-oriented march tests, which are very suitable for self-test applications, word-oriented extensions are presented and analyzed for fault coverage. The self-test algorithm gives a high fault coverage for digital faults. Besides simple stuck-at faults, it detects transition faults and multiple-access faults. Also, all two-coupling faults between arbitrary pairs of cells are detected, so no knowledge of the physical placement of the cells is required. A prototype of the hardware implementation of the BIST method shows that the overhead, especially for large RAMs, is quite modest. The self-test hardware can be parameterized to size, making automatic generation by a module compiler easy.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126435278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-11DOI: 10.1109/CMPEUR.1988.4960
P. Jamart, A. Baudhuin, M. Vandersmissen, M. Vanhoedenaghe
The authors propose a typing system for tools and objects based on the comparison of attributes that are associated with objects with expressions on these attributes that are associated with tools. This system allows static type checking of command lines having arguments that can be simple objects, structured objects, or families of objects. The concepts are general enough to be used not only in software development environments, but also in other CAD environments.<>
{"title":"A typing system for software development environments","authors":"P. Jamart, A. Baudhuin, M. Vandersmissen, M. Vanhoedenaghe","doi":"10.1109/CMPEUR.1988.4960","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4960","url":null,"abstract":"The authors propose a typing system for tools and objects based on the comparison of attributes that are associated with objects with expressions on these attributes that are associated with tools. This system allows static type checking of command lines having arguments that can be simple objects, structured objects, or families of objects. The concepts are general enough to be used not only in software development environments, but also in other CAD environments.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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