High coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost

Proceedings. 21st VLSI Test Symposium, 2003. Pub Date : 2003-04-27 DOI:10.1109/VTEST.2003.1197638

S. Bhattacharya, A. Chatterjee

引用次数: 5

Abstract

It is well known that wafer probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much as the testing process into wafer-probe lest as possible while limiting the scope of assembled package test. However, the signal drive and response observation capabilities during wafer probe lest are limited in comparison to assembled package test. In this paper, it is shown that by marginally increasing the capabilities of wafer probe lest equipment to include low-speed transient signals, significant numbers of bad ICs can be detected early during wafer probe lest. The optimal test stimulus is determined by co-optimizing the wafer-probe and assembled package test waveforms. Overall, test costs, including the cost of packaging bad ICs are minimized.

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高覆盖模拟晶圆探针测试设计和集成封装测试协同优化，以最大限度地降低整体测试成本

众所周知，模拟集成电路的晶圆探头测试成本比组装封装的相应测试成本低一个数量级。因此，在限制组装封装测试范围的同时，尽可能多地将测试过程推向晶圆探头是很自然的。然而，与组装封装测试相比，晶圆探针测试期间的信号驱动和响应观察能力受到限制。本文表明，通过略微增加晶圆探头检测设备的能力以包含低速瞬态信号，可以在晶圆探头检测期间早期检测到大量不良ic。通过对晶圆探针和组装封装测试波形的共同优化，确定了最优的测试刺激。总的来说，测试成本，包括封装坏ic的成本被最小化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. 21st VLSI Test Symposium, 2003.

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