Tara Prasanna Dash, J. Jena, E. Mohapatra, S. Dey, S. Das, C. K. Maiti
{"title":"Role of Stress/Strain Mapping in Advanced CMOS Process Technology Nodes","authors":"Tara Prasanna Dash, J. Jena, E. Mohapatra, S. Dey, S. Das, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783211","DOIUrl":null,"url":null,"abstract":"Multiple-gate MOSFETs have emerged as potential candidates for the future device generations considering the continuous increase in performance requirements. Therefore, a great demand to control strain/stress and their variation in MOSFETs has recently emerged. In this work, biaxial and uniaxial strain techniques are implemented in the device channel for both p- and n-type MOSFETs. Stress/strain mapping in strained-Si and SiGe channel trapezoidal tri-gate FinFET devices are studied through three-dimensional (3D) numerical simulation, with particular focus on enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Multiple-gate MOSFETs have emerged as potential candidates for the future device generations considering the continuous increase in performance requirements. Therefore, a great demand to control strain/stress and their variation in MOSFETs has recently emerged. In this work, biaxial and uniaxial strain techniques are implemented in the device channel for both p- and n-type MOSFETs. Stress/strain mapping in strained-Si and SiGe channel trapezoidal tri-gate FinFET devices are studied through three-dimensional (3D) numerical simulation, with particular focus on enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
