Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783300
Tara Prasanna Dash, S. Dey, E. Mohapatra, S. Das, J. Jena, C. K. Maiti
Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. With the end of happy scaling era, change of device architecture has raised integration complexity along with several sort channel effects, mobility degradation, variability and quantum tunneling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7nm technology nodes. Towards low power and high speed (More-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the question of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass the FinFETs. In this work, we use 3-D predictive simulations to study the performance potential of SNS-FETs at 3nm technology node.
{"title":"Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes","authors":"Tara Prasanna Dash, S. Dey, E. Mohapatra, S. Das, J. Jena, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783300","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783300","url":null,"abstract":"Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. With the end of happy scaling era, change of device architecture has raised integration complexity along with several sort channel effects, mobility degradation, variability and quantum tunneling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7nm technology nodes. Towards low power and high speed (More-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the question of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass the FinFETs. In this work, we use 3-D predictive simulations to study the performance potential of SNS-FETs at 3nm technology node.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122836244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783894
S. R. Panda, Sudhakar Das, A. Sahu, A. K. Panda, T. Sahu
Non-monotonic mobility $mu$ of electrons is obtained in a pseudomorphic GaAs/InxGa1-x As high electron mobility transistor having a double quantum well structure with asymmetric doping concentrations in the outer barriers. A dip in ${mu}$ occurs at the resonance of subband states because of the shift of the subband wave functions, which affects the subband mobilities limited by interface roughness scattering. The dip in $mu$ amplifies with increase in the asymmetry of the width of wells.
{"title":"Nonmonotonous Electron Mobility in Double Quantum Well Pseudomorphic High Electron Mobility Transistor Structure","authors":"S. R. Panda, Sudhakar Das, A. Sahu, A. K. Panda, T. Sahu","doi":"10.1109/DEVIC.2019.8783894","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783894","url":null,"abstract":"Non-monotonic mobility $mu$ of electrons is obtained in a pseudomorphic GaAs/InxGa1-x As high electron mobility transistor having a double quantum well structure with asymmetric doping concentrations in the outer barriers. A dip in ${mu}$ occurs at the resonance of subband states because of the shift of the subband wave functions, which affects the subband mobilities limited by interface roughness scattering. The dip in $mu$ amplifies with increase in the asymmetry of the width of wells.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783865
Akash Roy, Rajrup Mitra, A. Kundu
This paper elucidates a comprehensive, illustrative and qualitative study on the Analog and RF performance of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper presents the effect of GaN channel thickness variation on the drain current $pmb{(I_{d})}$, the transconductance $(g_{m})$, output resistance $pmb{(R_o)}$, the intrinsic gain $pmb{(g_{m}R_{o})}$, transconductance generation factor $(g_{m}/I_{d})$ and the RF FOMs- total intrinsic gate capacitance $(C_{gg})$ and cut-off frequency $(f_{T})$. These hetero-structured devices show superior performance as power transistors due to its enhanced efficiency, cost-effectiveness, reliability and controllability over silicon based conventional DG-MOS and HEMT transistors.
{"title":"Influence of Channel Thickness on Analog and RF Performance Enhancement of an Underlap DG AlGaN/GaN based MOS-HEMT Device","authors":"Akash Roy, Rajrup Mitra, A. Kundu","doi":"10.1109/DEVIC.2019.8783865","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783865","url":null,"abstract":"This paper elucidates a comprehensive, illustrative and qualitative study on the Analog and RF performance of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper presents the effect of GaN channel thickness variation on the drain current $pmb{(I_{d})}$, the transconductance $(g_{m})$, output resistance $pmb{(R_o)}$, the intrinsic gain $pmb{(g_{m}R_{o})}$, transconductance generation factor $(g_{m}/I_{d})$ and the RF FOMs- total intrinsic gate capacitance $(C_{gg})$ and cut-off frequency $(f_{T})$. These hetero-structured devices show superior performance as power transistors due to its enhanced efficiency, cost-effectiveness, reliability and controllability over silicon based conventional DG-MOS and HEMT transistors.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133423774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783866
S. Mohanty, S. Mishra, S. Mohanty, G. P. Mishra
Surrounding gate (SG) heterostructure metal oxide semiconductor field effect transistor (HMOSFET) has been embraced for generating the future device, which could limit the working range and decrease the static standby power dissipation. This paper presents an investigation of source $delta$ -doped In0.53Ga0.47 As /InP based SGHMOSFET to enhance the device performance. As the channel is encompassed by the all-around gate with the $delta$ -doped region in the source end, there is a better electrostatic control around the HMOSFET, which is obvious through the smaller DIBL and SS as compared to conventional SGHMOSFET. The proposed work deals with a detailed simulation based study of the device performance parameters such as the surface potential, electric field, electron mobility, On resistance, threshold voltage and drain current. The simulated results are compared with conventional SGHMOSFET. It has been revealed that $delta$ -doped SGHMOSFET gives a superior insusceptibility to short channel effects (SCEs) when compared with conventional SGHMOSFET.
围绕栅极(SG)异质结构金属氧化物半导体场效应晶体管(HMOSFET)被用于产生未来器件，它可以限制工作范围并降低静态待机功耗。为了提高器件性能，本文研究了源掺杂In0.53Ga0.47 As /InP的SGHMOSFET。由于通道被源端掺杂$ δ $区域的全栅极包围，因此HMOSFET周围的静电控制效果更好，这一点通过与传统SGHMOSFET相比更小的DIBL和SS可以明显看出。提出的工作涉及基于器件性能参数的详细仿真研究，如表面电位，电场，电子迁移率，On电阻，阈值电压和漏极电流。仿真结果与常规SGHMOSFET进行了比较。研究表明，与传统的SGHMOSFET相比，$delta$掺杂的SGHMOSFET对短通道效应(SCEs)具有更好的不敏感性。
{"title":"An extensive analysis of In0.53Ga0.47As/InP surrounding gate MOSFET to enhance the electrostatic performance using $delta$-doped technique","authors":"S. Mohanty, S. Mishra, S. Mohanty, G. P. Mishra","doi":"10.1109/DEVIC.2019.8783866","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783866","url":null,"abstract":"Surrounding gate (SG) heterostructure metal oxide semiconductor field effect transistor (HMOSFET) has been embraced for generating the future device, which could limit the working range and decrease the static standby power dissipation. This paper presents an investigation of source $delta$ -doped In0.53Ga0.47 As /InP based SGHMOSFET to enhance the device performance. As the channel is encompassed by the all-around gate with the $delta$ -doped region in the source end, there is a better electrostatic control around the HMOSFET, which is obvious through the smaller DIBL and SS as compared to conventional SGHMOSFET. The proposed work deals with a detailed simulation based study of the device performance parameters such as the surface potential, electric field, electron mobility, On resistance, threshold voltage and drain current. The simulated results are compared with conventional SGHMOSFET. It has been revealed that $delta$ -doped SGHMOSFET gives a superior insusceptibility to short channel effects (SCEs) when compared with conventional SGHMOSFET.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123562928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783566
S. Das, Tara Prasanna Dash, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti
Following the downscaling roadmap for planar MOSFETs, non-planar (3-D) multiple-gate architectures are becoming essential for ultimate scaling of CMOS devices. Negative bias temperature instability (NBTI) is one of the key device reliability issues which exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) have been investigated. When stressed, NBTI behavior in SNWTs show fast initial degradation, quick degradation saturation and then a special recovery behavior.
{"title":"NBTI Degradation and Recovery in Nanowire FETs","authors":"S. Das, Tara Prasanna Dash, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783566","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783566","url":null,"abstract":"Following the downscaling roadmap for planar MOSFETs, non-planar (3-D) multiple-gate architectures are becoming essential for ultimate scaling of CMOS devices. Negative bias temperature instability (NBTI) is one of the key device reliability issues which exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) have been investigated. When stressed, NBTI behavior in SNWTs show fast initial degradation, quick degradation saturation and then a special recovery behavior.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"77 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126018492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783574
Anirbit Sengupta, Tausif Mallick, Abhijit Das
People suffering from listening impairment and voice disability usually make use of different sign of symbols and languages for their communication purpose. Sign languages are generally dependent on hand-driven gesticulations with various motions explicit to that particular language by which these people communicate. In sign language, gesticulation is basically specific movements of our hands with an explicit form build out of them. Current research focuses on converting the hand gesticulations based on electronic devices. The devices will basically convert the sign language into its speech form to build the communication gap among the voiceless societies with the normal people. Here cloth driven gloves are being used which are Bluetooth-enabled. The glove is tailored with one accelerometer and five flexible sensors. The sensor placement is length ways of each of the fingers with the thumb. This work will facilitate the silent people to make different hand gesticulations wearing this gloves, and these intern will be transformed into respective speeches to the normal peoples recognition. In this case flexible sensors has a key role to play. Also the resistance value change generating from the extent of curvature of the sensors in combination with accelerometer value of slant position of hand to the land surface is measured. This acquired data is further managed by microcontroller module and can be transmitted to any smart-phone user via Bluetooth connectivity. A developed application can further be used to transform the data into text liable to the hand shape detected and will produce a voice signal.
{"title":"A Cost Effective Design and Implementation of Arduino Based Sign Language Interpreter","authors":"Anirbit Sengupta, Tausif Mallick, Abhijit Das","doi":"10.1109/DEVIC.2019.8783574","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783574","url":null,"abstract":"People suffering from listening impairment and voice disability usually make use of different sign of symbols and languages for their communication purpose. Sign languages are generally dependent on hand-driven gesticulations with various motions explicit to that particular language by which these people communicate. In sign language, gesticulation is basically specific movements of our hands with an explicit form build out of them. Current research focuses on converting the hand gesticulations based on electronic devices. The devices will basically convert the sign language into its speech form to build the communication gap among the voiceless societies with the normal people. Here cloth driven gloves are being used which are Bluetooth-enabled. The glove is tailored with one accelerometer and five flexible sensors. The sensor placement is length ways of each of the fingers with the thumb. This work will facilitate the silent people to make different hand gesticulations wearing this gloves, and these intern will be transformed into respective speeches to the normal peoples recognition. In this case flexible sensors has a key role to play. Also the resistance value change generating from the extent of curvature of the sensors in combination with accelerometer value of slant position of hand to the land surface is measured. This acquired data is further managed by microcontroller module and can be transmitted to any smart-phone user via Bluetooth connectivity. A developed application can further be used to transform the data into text liable to the hand shape detected and will produce a voice signal.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783736
S. Hungyo, Khomdram Jolson Singh, R. Dhar
A numerical modelling of highly efficient InGaP/GaAs dual-junction solar cell using advanced TCAD tool Silvaco ATLAS gives a theoretical conversion efficiency up to 31.08% at 1 sun under AM1.5 illumination. Within a temperature range from 0 to 150°C, the critical performance parameter such as $mathrm{J}_{mathrm{s}mathrm{c}}, mathrm{V}_{mathrm{o}mathrm{c}}$ and Photogeneration rates of this optimised cell were extracted. It is found that with the increase in the cell temperature, the sub cells quantum efficiencies increase slightly and due to the energy gap narrowing effect with increase in cell temperature, the red-shift phenomena of absorption limit for all sub cells are observed. It was also found that with increased in temperature, $mathrm{V}_{mathrm{o}mathrm{c}}$ decreases which are due to the increase in reverse saturation current, thereby leading to the decrease in the overall FF and efficiency of the solar cell. This work therefore calculates the optimum thickness of the modelled solar cell so that maximum efficiency is gained even if the temperature is elevated.
{"title":"Cell thickness optimization of dual junction InGaP/GaAs solar cell against temperature variation","authors":"S. Hungyo, Khomdram Jolson Singh, R. Dhar","doi":"10.1109/DEVIC.2019.8783736","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783736","url":null,"abstract":"A numerical modelling of highly efficient InGaP/GaAs dual-junction solar cell using advanced TCAD tool Silvaco ATLAS gives a theoretical conversion efficiency up to 31.08% at 1 sun under AM1.5 illumination. Within a temperature range from 0 to 150°C, the critical performance parameter such as $mathrm{J}_{mathrm{s}mathrm{c}}, mathrm{V}_{mathrm{o}mathrm{c}}$ and Photogeneration rates of this optimised cell were extracted. It is found that with the increase in the cell temperature, the sub cells quantum efficiencies increase slightly and due to the energy gap narrowing effect with increase in cell temperature, the red-shift phenomena of absorption limit for all sub cells are observed. It was also found that with increased in temperature, $mathrm{V}_{mathrm{o}mathrm{c}}$ decreases which are due to the increase in reverse saturation current, thereby leading to the decrease in the overall FF and efficiency of the solar cell. This work therefore calculates the optimum thickness of the modelled solar cell so that maximum efficiency is gained even if the temperature is elevated.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130527410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783308
Phuntso Chotten, Akho John Richa
A comparative study of a voltage mode sense amplifier (VMSA) using different techniques to understand their performance and applicability has been presented in this paper. The circuits to be studied are VMSA using a coupling capacitor and body biasing along with the conventional circuit. Various performance measuring parameters of the sense amplifiers (SA) have been examined and analyzed. It has been realized that both the techniques heighten the performance of the sense amplifier in comparison to the conventional method, but their mutual comparison reveals that the coupling capacitor has better performance than the body biasing technique. Detail analysis of the circuits in term of sensitivity, power consumption and delay has been made for a better understanding of their performances. The circuits in the paper have been simulated by using Tanner EDA tool of 0.25 um technology.
{"title":"Performance Comparison of Body Biasing and Coupling Capacitor Sense Amplifier for SRAM","authors":"Phuntso Chotten, Akho John Richa","doi":"10.1109/DEVIC.2019.8783308","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783308","url":null,"abstract":"A comparative study of a voltage mode sense amplifier (VMSA) using different techniques to understand their performance and applicability has been presented in this paper. The circuits to be studied are VMSA using a coupling capacitor and body biasing along with the conventional circuit. Various performance measuring parameters of the sense amplifiers (SA) have been examined and analyzed. It has been realized that both the techniques heighten the performance of the sense amplifier in comparison to the conventional method, but their mutual comparison reveals that the coupling capacitor has better performance than the body biasing technique. Detail analysis of the circuits in term of sensitivity, power consumption and delay has been made for a better understanding of their performances. The circuits in the paper have been simulated by using Tanner EDA tool of 0.25 um technology.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134103745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783229
K. Roy, C. Sarkar, C. Ghosh
Here, we demonstrated an easy, clean and eco-benign synthetic protocol for silver nanoparticle production from silver nitrate salt using Indian bay leaf (Cinnamomum tamala) extract. Production of silver nanoparticle was monitored at periodic intervals through ultra-violet visible spectroscopy (UV-Vis). X-ray powder diffraction (XRD) and high resolution electron microscopy (HRTEM) respectively indicated the crystal phases and shape of prepared nanoparticles. Infra-red spectroscopy (FTIR) of the nanoparticles revealed the role of functional organic molecules involved in surface capping and stabilization of the particles. Thin film of green synthesized silver nanoparticles was deposited carefully and then connected to regulated DC voltage to realize the conducting behaviour. The obtained result signified the semi-conductive behavior of silver thin film at ambient temperature.
{"title":"Semiconducting Behaviour of Metal Thin Film composed of Green Synthesized Silver Nanoparticles","authors":"K. Roy, C. Sarkar, C. Ghosh","doi":"10.1109/DEVIC.2019.8783229","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783229","url":null,"abstract":"Here, we demonstrated an easy, clean and eco-benign synthetic protocol for silver nanoparticle production from silver nitrate salt using Indian bay leaf (Cinnamomum tamala) extract. Production of silver nanoparticle was monitored at periodic intervals through ultra-violet visible spectroscopy (UV-Vis). X-ray powder diffraction (XRD) and high resolution electron microscopy (HRTEM) respectively indicated the crystal phases and shape of prepared nanoparticles. Infra-red spectroscopy (FTIR) of the nanoparticles revealed the role of functional organic molecules involved in surface capping and stabilization of the particles. Thin film of green synthesized silver nanoparticles was deposited carefully and then connected to regulated DC voltage to realize the conducting behaviour. The obtained result signified the semi-conductive behavior of silver thin film at ambient temperature.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"60 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133120622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783836
Supriti Samanta, G. Maity, Subhadipta Mukhopadhyay
Code division multiple access (CDMA) or multicarrier CDMA (MC-CDMA), Walsh-Hadamard codes are extensively used for its attribute of orthogonality and hence it leads to good cross-correlation property. In the last time, in CDMA communications, spread spectrum codes is Walsh-Hadamard codes and it is generated simply. Walsh-Hadamard codes are completely orthogonal binary user codes, that arehaving a lot of favorable applications in communications based on synchronous multicarrier. However, the optical applications of Walsh-Hadamard codes are also important for optical CDMA. To achieve this goal, all-optical Walsh-Hadamard codes generation using Mach-Zehnder interferometer (MZI) is explored in this paper.
{"title":"All-optical Walsh-Hadamard code Generation using MZI","authors":"Supriti Samanta, G. Maity, Subhadipta Mukhopadhyay","doi":"10.1109/DEVIC.2019.8783836","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783836","url":null,"abstract":"Code division multiple access (CDMA) or multicarrier CDMA (MC-CDMA), Walsh-Hadamard codes are extensively used for its attribute of orthogonality and hence it leads to good cross-correlation property. In the last time, in CDMA communications, spread spectrum codes is Walsh-Hadamard codes and it is generated simply. Walsh-Hadamard codes are completely orthogonal binary user codes, that arehaving a lot of favorable applications in communications based on synchronous multicarrier. However, the optical applications of Walsh-Hadamard codes are also important for optical CDMA. To achieve this goal, all-optical Walsh-Hadamard codes generation using Mach-Zehnder interferometer (MZI) is explored in this paper.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116261412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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