Verification of the speed-independent circuits by STG unfoldings

A. Kondratyev, A. Taubin
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引用次数: 19

Abstract

In this paper we show how to analyze an arbitrary STG for the speed-independence property. The idea of analysis is based on the STG unfolding into an acyclic graph. The improved method of unfolding is suggested, in which the size of the obtained description is always less (or equal in the case of a fully sequential process) than the size of a corresponding state graph. Based on this method the verification algorithms of STG analysis are developed. These algorithms are polynomial from the size of STG unfolding. Their efficiency is considered on the set of benchmarks.
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通过STG展开验证速度无关电路
本文给出了如何分析任意STG的速度无关性。分析的思想是基于STG展开成一个无环图。提出了一种改进的展开方法,在这种方法中,得到的描述的大小总是小于对应状态图的大小(在全顺序过程中是相等的)。在此基础上,开发了STG分析的验证算法。这些算法是从STG展开的大小的多项式。它们的效率是在一组基准上考虑的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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An asynchronous pipelined lattice structure filter Verification of the speed-independent circuits by STG unfoldings Designing asynchronous circuits from behavioural specifications with internal conflicts Tools for validating asynchronous digital circuits Sufficient conditions for correct gate-level speed-independent circuits
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