Simulation and measurement of thermal stress in quasi-monolithic integration technology (QMIT)

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220) Pub Date : 2001-05-29 DOI:10.1109/ECTC.2001.927811

M. Joodaki, G. Kompa, T. Leinhos, R. Kassing, H. Hillmer

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引用次数: 7

Abstract

It is well known that thermal stress not only effects the reliability and life time of the packaging but also the device characteristics, which is crucial in microwave and millimeter wave design. A three dimensional finite element (3DFE) thermal stress simulator, scanning probe microscopy (SPM) measurements and nanometer surface profiler (DEKTAK) accompanied with a Peltier element (PE) have been used to determine the thermal stress distribution in the standard structure of QMIT. In this method by measuring and mapping the surface profile of Si-wafer around the embedded devices using SPM and DEKTAK the induced thermal stress is determined. Effects of different parameters such as baking temperature, power dissipation of the embedded GaAs-FET, geometry and elastic properties of thermal conductive epoxy have been described in detail. In all simulations a new model of QMIT with a minimum-number of nodes has been introduced. Remarkable agreement between calculated and measured displacements created by thermal stress was found.

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准单片集成技术(QMIT)中热应力的模拟与测量

众所周知，热应力不仅影响封装的可靠性和寿命，而且影响器件的特性，这在微波和毫米波设计中至关重要。采用三维有限元(3DFE)热应力模拟器、扫描探针显微镜(SPM)测量和纳米表面轮廓仪(DEKTAK)以及Peltier单元(PE)对QMIT标准结构的热应力分布进行了分析。该方法利用SPM和DEKTAK测量和绘制嵌入器件周围硅片的表面轮廓，从而确定其诱导热应力。详细讨论了烘烤温度、嵌入式GaAs-FET的功耗、导热环氧树脂的几何形状和弹性性能等参数对其性能的影响。在所有的仿真中都引入了一个新的最小节点数QMIT模型。热应力引起的位移计算值与实测值非常吻合。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

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