Pub Date : 2002-08-07DOI: 10.1109/ECTC.2001.927962
M. J. Choi, A. Cangellaris
This paper describes a systematic methodology for the electromagnetic modeling of complex power distribution networks. The proposed methodology uses locally three-dimensional modifications to an otherwise two-dimensional description of the behavior of electromagnetic fields between power/ground plane pairs, to model correctly the field behavior at discontinuities such as vias, pins, as well as splits in the power/ground plane structure. Furthermore, a systematic synthesis methodology is presented for the direct generation of a SPICE-compatible multi-port macro-model for the power distribution network from its discrete quasi three-dimensional model. The proposed modeling and equivalent circuit synthesis methodologies are validated through a specific numerical simulation study of the transient electromagnetic analysis of a power/ground plane pair during switching.
{"title":"A quasi three-dimensional distributed electromagnetic model for complex power distribution networks","authors":"M. J. Choi, A. Cangellaris","doi":"10.1109/ECTC.2001.927962","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927962","url":null,"abstract":"This paper describes a systematic methodology for the electromagnetic modeling of complex power distribution networks. The proposed methodology uses locally three-dimensional modifications to an otherwise two-dimensional description of the behavior of electromagnetic fields between power/ground plane pairs, to model correctly the field behavior at discontinuities such as vias, pins, as well as splits in the power/ground plane structure. Furthermore, a systematic synthesis methodology is presented for the direct generation of a SPICE-compatible multi-port macro-model for the power distribution network from its discrete quasi three-dimensional model. The proposed modeling and equivalent circuit synthesis methodologies are validated through a specific numerical simulation study of the transient electromagnetic analysis of a power/ground plane pair during switching.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126307580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927973
Jiansen Zhu, S. Quander, T. Reinikainen
PWB assemblies are sometimes subjected to mechanical loading during their lifetime, which will cause PWB deflection and stress/strain in the assemblies. These mechanical loads may be either monotonic or cyclic. For example, assembling force may cause PWB deformation if the PWB has an initial warpage and key striking may apply a cyclic load to PWB. These mechanical loadings will increase stress/strain level inside PWB and may have an effect on interconnect, PWB, or package reliability. In order to evaluate the reliability of PWB assembly, a global/local modeling methodology was developed. In this method, a PWB with micro-scale BGAs is modeled as a global model with relatively coarse mesh, which is used to capture the deformation of PWB under mechanical loading. Both the critical package and critical solder joint can also be located based on the stress/strain distribution obtained from this global model prediction. Then the critical package is modeled as a local model with a fine mesh to capture the details of packages and interconnects. In this study, solder joints of micro-scale BGAs are modeled in detail in order to capture the detail stress/strain distribution. The deformation captured by the global model is transferred to the local model as boundary conditions. Finally, a strain energy based reliability model is proposed to estimate the life of solder joints under cyclic mechanical loading and this model was calibrated by the experimental data.
{"title":"Global/local modeling for PWB mechanical loading","authors":"Jiansen Zhu, S. Quander, T. Reinikainen","doi":"10.1109/ECTC.2001.927973","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927973","url":null,"abstract":"PWB assemblies are sometimes subjected to mechanical loading during their lifetime, which will cause PWB deflection and stress/strain in the assemblies. These mechanical loads may be either monotonic or cyclic. For example, assembling force may cause PWB deformation if the PWB has an initial warpage and key striking may apply a cyclic load to PWB. These mechanical loadings will increase stress/strain level inside PWB and may have an effect on interconnect, PWB, or package reliability. In order to evaluate the reliability of PWB assembly, a global/local modeling methodology was developed. In this method, a PWB with micro-scale BGAs is modeled as a global model with relatively coarse mesh, which is used to capture the deformation of PWB under mechanical loading. Both the critical package and critical solder joint can also be located based on the stress/strain distribution obtained from this global model prediction. Then the critical package is modeled as a local model with a fine mesh to capture the details of packages and interconnects. In this study, solder joints of micro-scale BGAs are modeled in detail in order to capture the detail stress/strain distribution. The deformation captured by the global model is transferred to the local model as boundary conditions. Finally, a strain energy based reliability model is proposed to estimate the life of solder joints under cyclic mechanical loading and this model was calibrated by the experimental data.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124385122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927745
J. Grzyb, D. Cottet, G. Troster
Recently, there was significant growth in wireless telecommunication applications such as Cellular and Mobile phones, Personal Communication System, Wireless Local Area Network, Pagers, Global Positioning Satellite communication, etc. In future, telecommunication applications will shift more and more to the use of higher frequencies. Multichip Modules (MCMs) and MCM technologies are very close to micro- and millimeter-wave systems like transmitter/receiver (T/R) for radars and communication modules for wireless infrastructure links. There are various stringent requirements for MCMs in this frequency range but one of the most critical requirements is the ability of high RF performance together with high yield and low cost high volume production. Integration of RF circuits and elements with digital and analog circuits on the same substrate is essential to reduce the overall cost and physical dimensions of the whole system. The integrated antenna T/R is a very interesting alternative for applications where compact design, low cost, and high volume are important factors. Integration of the antenna in such a module is very difficult because the technological requirements driven by its performance characteristics (radiation efficiency, bandwidth) are opposite to these of non-radiating elements, where the radiation effect is not desirable. This issue is especially important for low-profile build-up MCM-D technologies where the problem of radiation efficiency of microstrip antennas is extremely difficult to solve. This paper will discuss the EM based modelling and practical design of microstrip and novel slot antennas in the mm-wave frequency range (30-85 GHz) on low cost MCM-D substrates. The critical parameters of millimeter design such as losses, bandwidth, and radiation pattern will be discussed. To perform this feasibility study a finite element method (FEM) is used as a simulation tool and HP8510XF Vector Network Analyzer (VNA) as a measurement equipment.
{"title":"mm-wave microstrip and novel slot antennas on low cost large area panel MCM-D substrates-a feasibility and performance study","authors":"J. Grzyb, D. Cottet, G. Troster","doi":"10.1109/ECTC.2001.927745","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927745","url":null,"abstract":"Recently, there was significant growth in wireless telecommunication applications such as Cellular and Mobile phones, Personal Communication System, Wireless Local Area Network, Pagers, Global Positioning Satellite communication, etc. In future, telecommunication applications will shift more and more to the use of higher frequencies. Multichip Modules (MCMs) and MCM technologies are very close to micro- and millimeter-wave systems like transmitter/receiver (T/R) for radars and communication modules for wireless infrastructure links. There are various stringent requirements for MCMs in this frequency range but one of the most critical requirements is the ability of high RF performance together with high yield and low cost high volume production. Integration of RF circuits and elements with digital and analog circuits on the same substrate is essential to reduce the overall cost and physical dimensions of the whole system. The integrated antenna T/R is a very interesting alternative for applications where compact design, low cost, and high volume are important factors. Integration of the antenna in such a module is very difficult because the technological requirements driven by its performance characteristics (radiation efficiency, bandwidth) are opposite to these of non-radiating elements, where the radiation effect is not desirable. This issue is especially important for low-profile build-up MCM-D technologies where the problem of radiation efficiency of microstrip antennas is extremely difficult to solve. This paper will discuss the EM based modelling and practical design of microstrip and novel slot antennas in the mm-wave frequency range (30-85 GHz) on low cost MCM-D substrates. The critical parameters of millimeter design such as losses, bandwidth, and radiation pattern will be discussed. To perform this feasibility study a finite element method (FEM) is used as a simulation tool and HP8510XF Vector Network Analyzer (VNA) as a measurement equipment.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"83 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126076054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927732
A. Syed
Solder joint reliability has received a renewed interest since the inception of BGA and CSP type packages. While traditionally board level reliability during thermal and power cycling is considered important for most applications, solder joint failures due to board bending have also become a major reliability concern for portable applications. With the current trend of cheaper, faster, and better electronic equipment, it has become increasingly important to evaluate the package and system performance very early in the design cycle using simulation tools. Although a number of life prediction models for solder joint under thermal cycle conditions have been proposed in the literature, not enough work has been reported in extending these models to power and bend cycle simulations. The accuracy of life prediction tool has also become critically important, as the designs need to be evaluated and improved with high degree of confidence not through relative comparison but by providing absolute numbers. This paper describes in detail the life prediction model for solder joints for thermal cycle conditions and its extension to power and bend, cycle conditions. The approach uses advance finite element modeling and analysis techniques such as constraint equations and sub-structuring and is based on mechanics of deformation. The model has been correlated with more than 60 data points and predicts life within 25% in most cases. The framework of modeling and prediction methodology described here is fully applicable for developing life prediction models for Pb free solder also, once the deformation mechanisms are identified.
{"title":"Predicting solder joint reliability for thermal, power, and bend cycle within 25% accuracy","authors":"A. Syed","doi":"10.1109/ECTC.2001.927732","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927732","url":null,"abstract":"Solder joint reliability has received a renewed interest since the inception of BGA and CSP type packages. While traditionally board level reliability during thermal and power cycling is considered important for most applications, solder joint failures due to board bending have also become a major reliability concern for portable applications. With the current trend of cheaper, faster, and better electronic equipment, it has become increasingly important to evaluate the package and system performance very early in the design cycle using simulation tools. Although a number of life prediction models for solder joint under thermal cycle conditions have been proposed in the literature, not enough work has been reported in extending these models to power and bend cycle simulations. The accuracy of life prediction tool has also become critically important, as the designs need to be evaluated and improved with high degree of confidence not through relative comparison but by providing absolute numbers. This paper describes in detail the life prediction model for solder joints for thermal cycle conditions and its extension to power and bend, cycle conditions. The approach uses advance finite element modeling and analysis techniques such as constraint equations and sub-structuring and is based on mechanics of deformation. The model has been correlated with more than 60 data points and predicts life within 25% in most cases. The framework of modeling and prediction methodology described here is fully applicable for developing life prediction models for Pb free solder also, once the deformation mechanisms are identified.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123691644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927909
Tay Hui Leng, Galen Kirkpatrick, A. Tay, Lu Li
In flip chip interconnection using eutectic Pb/Sn solder bumps, a highly reliable underbump metallization (UBM) is required to maintain adhesion and solder wettability. An experimental study investigated the thermal stability of the Cr/Cu/Ni UBM-where Cr act as an adhesive, Cu a solder wettable layer and Ni a barrier. The process window for good thermal stability will reduce silicon cratering failure and intermetallic failure to ensure reliability. The Cu and Ni layers were varied in low, medium and high thickness to study their impact on solder bump strength and failure mechanisms. 5/spl times/3 mm full array test chips (with Cr/Cu/Ni UBM) were subjected to thermal stability tests (1) multiple reflow for 1x, 5x, 10x, 20x and (2) high temperature storage at 150/spl deg/C up to 1000 hrs. Destructive ball shear test and cross-sectional analysis was done. Bump shear results show that the Cr/Cu/Ni UBM, with Ni thickness (low to high) remains stable with respect to the number of reflow cycles. The failures were cohesive (Mode I-within solder). A high Ni thickness inhibited Cu diffusion and suppressed Cu IMC formation at near solder interface. Under high temperature storage, intermetallic growth was accelerated and the excessive intermetallic formed was very brittle. For low Ni thickness, failure mode (Mode I+ Mode II) was observed after aging (>500 hrs). Failure mode remained as cohesive in high Ni thickness UBM. For low to high thickness Cu mini-bumps, shear strength was maintained during multiple reflows and the shearing fracture remains within the solder. Failure mode shifted from Mode I (at t=0) to Mode III interfacial failure (after aging) in Cr/low thickness Cu/medium thickness Ni UBM, when the limited Cu supply led to solder dewetting.
{"title":"Cr/Cu/Ni underbump metallization study","authors":"Tay Hui Leng, Galen Kirkpatrick, A. Tay, Lu Li","doi":"10.1109/ECTC.2001.927909","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927909","url":null,"abstract":"In flip chip interconnection using eutectic Pb/Sn solder bumps, a highly reliable underbump metallization (UBM) is required to maintain adhesion and solder wettability. An experimental study investigated the thermal stability of the Cr/Cu/Ni UBM-where Cr act as an adhesive, Cu a solder wettable layer and Ni a barrier. The process window for good thermal stability will reduce silicon cratering failure and intermetallic failure to ensure reliability. The Cu and Ni layers were varied in low, medium and high thickness to study their impact on solder bump strength and failure mechanisms. 5/spl times/3 mm full array test chips (with Cr/Cu/Ni UBM) were subjected to thermal stability tests (1) multiple reflow for 1x, 5x, 10x, 20x and (2) high temperature storage at 150/spl deg/C up to 1000 hrs. Destructive ball shear test and cross-sectional analysis was done. Bump shear results show that the Cr/Cu/Ni UBM, with Ni thickness (low to high) remains stable with respect to the number of reflow cycles. The failures were cohesive (Mode I-within solder). A high Ni thickness inhibited Cu diffusion and suppressed Cu IMC formation at near solder interface. Under high temperature storage, intermetallic growth was accelerated and the excessive intermetallic formed was very brittle. For low Ni thickness, failure mode (Mode I+ Mode II) was observed after aging (>500 hrs). Failure mode remained as cohesive in high Ni thickness UBM. For low to high thickness Cu mini-bumps, shear strength was maintained during multiple reflows and the shearing fracture remains within the solder. Failure mode shifted from Mode I (at t=0) to Mode III interfacial failure (after aging) in Cr/low thickness Cu/medium thickness Ni UBM, when the limited Cu supply led to solder dewetting.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928019
T. Troianello
The proliferation of airbags and other pyro-technically deployed safety devices in new cars will require a costly increase in the number of energy-storage devices needed for each vehicle. If the activation energy could be reduced, cheaper storage capacitors can be used. However, the low energy levels contemplated would reduce the diameter of the resistance wire traditionally used to initiate the pyro-technic chain that results in airbag deployment. The wire diameter then becomes so thin that it introduces numerous problems, all of which reduce reliability in critical safety systems. Foil resistors, in which a thin planar foil is supported on a substrate and etched to precise thermal and electrical specifications, were developed and tested to replace traditional initiators for low energy applications. This paper describes the products developed, the affect on associated concerns within the industry, and the reliability tests performed on low energy foil initiators.
{"title":"Precision foil resistors used as electro-pyrotechnic initiators","authors":"T. Troianello","doi":"10.1109/ECTC.2001.928019","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928019","url":null,"abstract":"The proliferation of airbags and other pyro-technically deployed safety devices in new cars will require a costly increase in the number of energy-storage devices needed for each vehicle. If the activation energy could be reduced, cheaper storage capacitors can be used. However, the low energy levels contemplated would reduce the diameter of the resistance wire traditionally used to initiate the pyro-technic chain that results in airbag deployment. The wire diameter then becomes so thin that it introduces numerous problems, all of which reduce reliability in critical safety systems. Foil resistors, in which a thin planar foil is supported on a substrate and etched to precise thermal and electrical specifications, were developed and tested to replace traditional initiators for low energy applications. This paper describes the products developed, the affect on associated concerns within the industry, and the reliability tests performed on low energy foil initiators.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126765930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927714
P. Miao, Y. Chew, Tie Wang, L. Foo
This paper presents two flip-chip assembly processes that enable an underfill with higher filler loading to be incorporated into the package. The first process includes dispensing the underfill containing higher filler loading on substrate surface, followed by chip placement and solder reflow under thermal compression. Apart from this, the second approach is virtually the modification of standard reflowable underfill process. The underfill with higher filler loading was spin-coated onto a bumped wafer surface and then cured. Subsequently, the top portion of bumps was exposed by laser treatment prior to wafer dicing. The diced chips with low CTE coating on the surface already were assembled via standard reflowable underfill process that includes dispensing reflowable underfill, chip placement and solder reflow through reflow oven.
{"title":"Flip-chip assembly development via modified reflowable underfill process","authors":"P. Miao, Y. Chew, Tie Wang, L. Foo","doi":"10.1109/ECTC.2001.927714","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927714","url":null,"abstract":"This paper presents two flip-chip assembly processes that enable an underfill with higher filler loading to be incorporated into the package. The first process includes dispensing the underfill containing higher filler loading on substrate surface, followed by chip placement and solder reflow under thermal compression. Apart from this, the second approach is virtually the modification of standard reflowable underfill process. The underfill with higher filler loading was spin-coated onto a bumped wafer surface and then cured. Subsequently, the top portion of bumps was exposed by laser treatment prior to wafer dicing. The diced chips with low CTE coating on the surface already were assembled via standard reflowable underfill process that includes dispensing reflowable underfill, chip placement and solder reflow through reflow oven.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126931020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927796
Jongwoon Park, J. Taweeplengsangsuke, C. Theis, J. Osenbach
The cure kinetics of a bisphenol epoxy system commonly used in optical fiber assembly and passive component has been analyzed by using a modulated dual scanning calorimeter (MDSC) under isothermal and dynamic conditions. The kinetic data are well represented by a two-parameter autocatalytical reaction rate model. The results suggest that curing of the bisphenol epoxy with imidazole as a curing agent can be fast cured at higher-temperatures. However, the size and numbers of voids increase as the isothermal cure temperature increases indicating that a high temperature snap cure may not provide adequate long term reliability and or fiber pull strength. Based on the thermogravimetric analysis (TGA) results we developed a step cure process for curing the epoxy. On a comparative basis we have found that the site and density of voids at epoxy to plate glass interfaces after a step cure is less than that of after isothermal cures. For the purpose of the verification, fiber assemblies were, prepared by using different curing profiles. Some of these assemblies were cross-sectioned for optical microscopy for estimation of void density before and after temperature cycles, for other fiber assemblies the pull strength before and after temperature cycling was determined. We observed a significant decrease in the void density for the step-cured samples as compared to the isothermal cured samples. The average destructive fiber pull test after temperature cycle testing for the step cured assemblies is higher than the as made isothermal cure assemblies. The results indicate that a proper curing profile can restrict void formation and increase adhesion strength. Finally, we found that a two-parameter Frechet cumulative distribution function (cdf) could be used to represent the statistical behavior of the void distributions in the epoxy used in the fiber assemblies.
{"title":"Epoxy adhesive used in optical fiber/passive component: kinetics, voids and reliability","authors":"Jongwoon Park, J. Taweeplengsangsuke, C. Theis, J. Osenbach","doi":"10.1109/ECTC.2001.927796","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927796","url":null,"abstract":"The cure kinetics of a bisphenol epoxy system commonly used in optical fiber assembly and passive component has been analyzed by using a modulated dual scanning calorimeter (MDSC) under isothermal and dynamic conditions. The kinetic data are well represented by a two-parameter autocatalytical reaction rate model. The results suggest that curing of the bisphenol epoxy with imidazole as a curing agent can be fast cured at higher-temperatures. However, the size and numbers of voids increase as the isothermal cure temperature increases indicating that a high temperature snap cure may not provide adequate long term reliability and or fiber pull strength. Based on the thermogravimetric analysis (TGA) results we developed a step cure process for curing the epoxy. On a comparative basis we have found that the site and density of voids at epoxy to plate glass interfaces after a step cure is less than that of after isothermal cures. For the purpose of the verification, fiber assemblies were, prepared by using different curing profiles. Some of these assemblies were cross-sectioned for optical microscopy for estimation of void density before and after temperature cycles, for other fiber assemblies the pull strength before and after temperature cycling was determined. We observed a significant decrease in the void density for the step-cured samples as compared to the isothermal cured samples. The average destructive fiber pull test after temperature cycle testing for the step cured assemblies is higher than the as made isothermal cure assemblies. The results indicate that a proper curing profile can restrict void formation and increase adhesion strength. Finally, we found that a two-parameter Frechet cumulative distribution function (cdf) could be used to represent the statistical behavior of the void distributions in the epoxy used in the fiber assemblies.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115052924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927679
B. Keser, B. Yeung, J. White, T. Fang
A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8/spl times/8 array of bumps on a 5/spl times/5 mm/sup 2/ die. Micro Moire Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported.
{"title":"Encapsulated double-bump WL-CSP: design and reliability","authors":"B. Keser, B. Yeung, J. White, T. Fang","doi":"10.1109/ECTC.2001.927679","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927679","url":null,"abstract":"A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8/spl times/8 array of bumps on a 5/spl times/5 mm/sup 2/ die. Micro Moire Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115255576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927974
R. Ghaffarian
A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of CSPs for a variety of projects. The experience of the Consortium in building more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and the environmental test results has now been published as a CSP guidelines document. The Consortium assembled fifteen different packages with I/Os from 48 to 784 and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring board (PWB). Another test vehicle was designed and assembled by a team member using their internal resources and was identified as TV-H. The TV-H assemblies were subjected to numerous thermal cycling conditions including -55/spl deg/C to 125/spl deg/C with two ramp rates, one thermal cycle with 2/spl deg/ to 5/spl deg/C/min and the other near thermal shock. Cycles-to-failure (CTF) test results to 1,000 cycles and 400 cycles under these conditions are presented for fine pitch ball grid arrays (FPBGAs), CSPs, and wafer level CSPs (WLCSPs). Decrease in CTFs due to ramp rate and die size increase for different I/O FPBGAs with 0.8 mm pitch are compared and analyzed.
{"title":"Effect of thermal cycling ramp rate on CSP assembly reliability","authors":"R. Ghaffarian","doi":"10.1109/ECTC.2001.927974","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927974","url":null,"abstract":"A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of CSPs for a variety of projects. The experience of the Consortium in building more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and the environmental test results has now been published as a CSP guidelines document. The Consortium assembled fifteen different packages with I/Os from 48 to 784 and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring board (PWB). Another test vehicle was designed and assembled by a team member using their internal resources and was identified as TV-H. The TV-H assemblies were subjected to numerous thermal cycling conditions including -55/spl deg/C to 125/spl deg/C with two ramp rates, one thermal cycle with 2/spl deg/ to 5/spl deg/C/min and the other near thermal shock. Cycles-to-failure (CTF) test results to 1,000 cycles and 400 cycles under these conditions are presented for fine pitch ball grid arrays (FPBGAs), CSPs, and wafer level CSPs (WLCSPs). Decrease in CTFs due to ramp rate and die size increase for different I/O FPBGAs with 0.8 mm pitch are compared and analyzed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115581694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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