A high speed CMOS buffer for driving large capacitive loads in digital ASICs

Abstract

A High Speed High-Drive (HD) CMOS buffer is described in this paper which is an alternative to the widely used CMOS tapered buffer. The paper introduces the principle of operation of the HD buffer and compares it with a tapered buffer. Depending upon the capacitive load, the HD buffer as compared to an equivalent tapered buffer can provide increased speed (up to 2.2/spl times/) or multiple speed/power/area trade-offs. Clock distribution networks, large data buses, and I/O buffers are some possible applications of this buffer structure.