Design of CMOS programmable output binary and fibonacci switched capacitor step-down DC-DC converter

Abstract

This paper describes the CMOS implementation of an open-loop variable output voltage switched capacitor step-down DC-DC converter with a large number of target voltages. The number of target voltages generated using n-flying capacitors are of the order of 2n. A switch selection scheme is presented that optimizes silicon area. Expressions for equivalent series resistance Req, conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The Digital Switch Controller is designed to switch between various target voltages and simulated in Cadence Analog-Mixed Signal flow. The 3/4 step-down converter circuit is described and analysed by varying switching frequency and load for different values of bottom plate parasitic capacitance. The optimum value of switching frequency and switch sizes is obtained for a switched capacitor converter. An efficiency of about 78.4% is achieved with 5% bottom plate parasitic capacitance for a load current of 1.35 mA and input voltage of 1.8 V at 20 MHz of switching frequency.