{"title":"FPGA Based Implementation of MSOVA for CDMA2000 Turbo Decoder","authors":"A.M. Ismail, M. Nafie","doi":"10.1109/IWSOC.2006.348268","DOIUrl":null,"url":null,"abstract":"Soft output Viterbi algorithm (SOVA) and max-log-maximum a posteriori (Max-Log-MAP) are used for turbo codes decoding. SOVA is considered a simple way of implementation with higher throughput in comparison to the Max-Log-MAP, while the later is still superior from decoding performance point of view. A modified SOVA (MSOVA) was theoretically proven to be equivalent to Max-Log-MAP. In this paper a HW implementation for CDMA2000 turbo decoder using MSOVA is presented. This implementation is based on the MSOVA, using Xilinx Virtex 2 pro FPGA. The implementation was shown to have higher throughput and lower latency than a commercial decoder","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"168 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 6th International Workshop on System on Chip for Real Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2006.348268","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Soft output Viterbi algorithm (SOVA) and max-log-maximum a posteriori (Max-Log-MAP) are used for turbo codes decoding. SOVA is considered a simple way of implementation with higher throughput in comparison to the Max-Log-MAP, while the later is still superior from decoding performance point of view. A modified SOVA (MSOVA) was theoretically proven to be equivalent to Max-Log-MAP. In this paper a HW implementation for CDMA2000 turbo decoder using MSOVA is presented. This implementation is based on the MSOVA, using Xilinx Virtex 2 pro FPGA. The implementation was shown to have higher throughput and lower latency than a commercial decoder