Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348221
A. Gawanmeh, S. Tahar, A. Habibi
This paper proposes a methodology to integrate the property specification language (PSL) in the verification process of systems designed using abstract states machines (ASMs). A specification of PSL in ASM was provided, which allows us to integrate PSL properties as part of the design. For the verification, a technique based on the AsmL tool was proposed that translates the ASM code (containing both the design and the properties) into a finite state machine (FSM) representation. The generated FSM was used to run model checking on an external tool, here SMV. The approach takes advantage from the ASM language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C# code and an FSM representation from an ASM model. The approach was applied on SystemC designs, which are translated into ASM models. Experimental results on a bus structure from the SystemC library showed a superiority of the approach to conventional verification
{"title":"Embedding and Verification of PSL using ASM","authors":"A. Gawanmeh, S. Tahar, A. Habibi","doi":"10.1109/IWSOC.2006.348221","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348221","url":null,"abstract":"This paper proposes a methodology to integrate the property specification language (PSL) in the verification process of systems designed using abstract states machines (ASMs). A specification of PSL in ASM was provided, which allows us to integrate PSL properties as part of the design. For the verification, a technique based on the AsmL tool was proposed that translates the ASM code (containing both the design and the properties) into a finite state machine (FSM) representation. The generated FSM was used to run model checking on an external tool, here SMV. The approach takes advantage from the ASM language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C# code and an FSM representation from an ASM model. The approach was applied on SystemC designs, which are translated into ASM models. Experimental results on a bus structure from the SystemC library showed a superiority of the approach to conventional verification","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123119635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348228
Y. Massoud, M. Alam, A. Nieuwoudt
As process technology continues to scale into the nanoscale regime, passive components and interconnect plays an ever increasing role in realization of mixed-signal systems. In this paper, the authors develop a new method for the model order reduction of passive components and interconnect using frequency selective projection methods with interpolation points based on the spectral-zeros of the RLC interconnect model's transfer function. The methodology uses imaginary part of the spectral zeros for frequency selective adaptive projection and provides stable as well as passive reduced order models. The results indicate that our method provides more accurate approximations than techniques based on balanced truncation and moment matching
{"title":"On the Selection of Spectral Zeros for Generating Passive Reduced Order Models","authors":"Y. Massoud, M. Alam, A. Nieuwoudt","doi":"10.1109/IWSOC.2006.348228","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348228","url":null,"abstract":"As process technology continues to scale into the nanoscale regime, passive components and interconnect plays an ever increasing role in realization of mixed-signal systems. In this paper, the authors develop a new method for the model order reduction of passive components and interconnect using frequency selective projection methods with interpolation points based on the spectral-zeros of the RLC interconnect model's transfer function. The methodology uses imaginary part of the spectral zeros for frequency selective adaptive projection and provides stable as well as passive reduced order models. The results indicate that our method provides more accurate approximations than techniques based on balanced truncation and moment matching","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348266
M. Hamad, A. Kassem, R. Jabr, C. Bechara, M. Khattar
Teaching undergraduate electrical and computer engineering students microcontroller/microprocessor design concepts is essential in today's highly advanced technological environment. Furthermore, the authors believe that all engineering students should take an introductory course in this area. With this objective in mind, a PIC-based microcontroller design laboratory was developed. This Laboratory consists of a development board based on PIC16F877A microcontroller from microchip, essential software routines, and a laboratory manual that contains a list of design-applications experiments
{"title":"A PIC-Based Microcontroller Design Laboratory","authors":"M. Hamad, A. Kassem, R. Jabr, C. Bechara, M. Khattar","doi":"10.1109/IWSOC.2006.348266","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348266","url":null,"abstract":"Teaching undergraduate electrical and computer engineering students microcontroller/microprocessor design concepts is essential in today's highly advanced technological environment. Furthermore, the authors believe that all engineering students should take an introductory course in this area. With this objective in mind, a PIC-based microcontroller design laboratory was developed. This Laboratory consists of a development board based on PIC16F877A microcontroller from microchip, essential software routines, and a laboratory manual that contains a list of design-applications experiments","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"655 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348264
F. Besuzzi, A. Dassatti, G. Masera
Powerful channel codes are employed in modern communication systems in order to achieve very high data rates over noisy channels. The extremely low bit error rate (BER) reached by these codes requires that a huge number of samples are simulated to validate the system design. In addition simulation time is often made excessively long by the high computational complexity of addressed decoding algorithms and by the need of exploring the effect of code performance of different implementation choices (including finite precision representation of input and internal data), channel noise, fading and interferences. The use of software simulators may result in unacceptably long times and more cost effective solutions are required. This paper describes the design and the implementation of a new platform for accelerating channel codes simulations: a novel approach based on a mixed hardware-software design is described. The proposal ensures a wide range of flexibility and a significant reduction of the simulation time exploiting modern FPGAs characteristics
{"title":"Accelerating channel codes simulations with a mixed hardware-software system architecture","authors":"F. Besuzzi, A. Dassatti, G. Masera","doi":"10.1109/IWSOC.2006.348264","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348264","url":null,"abstract":"Powerful channel codes are employed in modern communication systems in order to achieve very high data rates over noisy channels. The extremely low bit error rate (BER) reached by these codes requires that a huge number of samples are simulated to validate the system design. In addition simulation time is often made excessively long by the high computational complexity of addressed decoding algorithms and by the need of exploring the effect of code performance of different implementation choices (including finite precision representation of input and internal data), channel noise, fading and interferences. The use of software simulators may result in unacceptably long times and more cost effective solutions are required. This paper describes the design and the implementation of a new platform for accelerating channel codes simulations: a novel approach based on a mixed hardware-software design is described. The proposal ensures a wide range of flexibility and a significant reduction of the simulation time exploiting modern FPGAs characteristics","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124334617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348254
I. Amer, A. Chirila-Rus, Wael Badawy, G. Jullien
The latest video standards such as ITU-T H.264 and MPEG-4 Part 10 introduce important bitrate gains but at the cost or increased complexity, especially at the encoder. One important tool is the variable block sizes motion estimation/compensation, which presents the possibility of using blocks ranging from 16times16 down to 4times4, offering the choice of one macroblock configuration out of 259 modes. This paper suggests a new method to select efficiently one variable block sizes partitioning mode based on a single set of motion estimation results at the smallest granularity (4times4 blocks). The results show the accuracy of the decision method, while requiring a minimal number of searches from the motion estimation algorithm. The technique also maintains an acceptable complexity for a potential real time implementation
最新的视频标准，如ITU-T H.264和MPEG-4 Part 10引入了重要的比特率增益，但代价是增加了复杂性，尤其是在编码器方面。一个重要的工具是可变块大小运动估计/补偿，它提供了使用块范围从16times16到4times4的可能性，提供了259种模式中的一种宏块配置选择。本文提出了一种基于最小粒度(4times4块)单组运动估计结果高效选择一种可变块大小划分模式的新方法。实验结果表明，该决策方法具有较高的准确性，且对运动估计算法的搜索次数要求较低。该技术还为潜在的实时实现保持了可接受的复杂性
{"title":"An Efficent Variable Block Size Selection Scheme for the H.264 Motion Estimation","authors":"I. Amer, A. Chirila-Rus, Wael Badawy, G. Jullien","doi":"10.1109/IWSOC.2006.348254","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348254","url":null,"abstract":"The latest video standards such as ITU-T H.264 and MPEG-4 Part 10 introduce important bitrate gains but at the cost or increased complexity, especially at the encoder. One important tool is the variable block sizes motion estimation/compensation, which presents the possibility of using blocks ranging from 16times16 down to 4times4, offering the choice of one macroblock configuration out of 259 modes. This paper suggests a new method to select efficiently one variable block sizes partitioning mode based on a single set of motion estimation results at the smallest granularity (4times4 blocks). The results show the accuracy of the decision method, while requiring a minimal number of searches from the motion estimation algorithm. The technique also maintains an acceptable complexity for a potential real time implementation","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132666553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348222
Chi-Ho Lin, Jin-Chun Kim
This paper presents a new VHDL intermediate format CDFG (control data flow graph) and a minimal hardware resource scheduling algorithm for ASIC design automation. The intermediate format, CDFG represents the constraints which limit hardware design such as conditional branch, sequential operation and time constraints. The proposed scheduling algorithm could handle the conditional branches effectively and could check the timing constraints efficiently. It minimizes the total operating time by reducing the number of the constraints as maximal as possible, determining the number of control steps in minimum bound. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples
{"title":"A Novel Scheduling methodology for ASIC Design","authors":"Chi-Ho Lin, Jin-Chun Kim","doi":"10.1109/IWSOC.2006.348222","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348222","url":null,"abstract":"This paper presents a new VHDL intermediate format CDFG (control data flow graph) and a minimal hardware resource scheduling algorithm for ASIC design automation. The intermediate format, CDFG represents the constraints which limit hardware design such as conditional branch, sequential operation and time constraints. The proposed scheduling algorithm could handle the conditional branches effectively and could check the timing constraints efficiently. It minimizes the total operating time by reducing the number of the constraints as maximal as possible, determining the number of control steps in minimum bound. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348257
DaeOk Kim, E. Jung, Hyunho Park, Hosoon Shin, D. Har
Context-based adaptive variable length coding (CAVLC) is entropy coding for H.264/AVC video codec. Since the CAVLC is highly context-adaptive and of a block-based context formation, high coding efficiency is achieved. However, its high complexity causes various difficulties in full-hardware implementation. This paper presents high performance hardware architecture of CAVLC. The proposed architecture is implemented in a FPGA device, and verified by RTL simulations. The implementation results show that the proposed architecture encodes a 4times4 block per 16 clock cycles, and achieves a real-time processing for 1920times1088 frame size with 30-fps video at 100MHz clock speed
{"title":"Implementation of High Performance CAVLC for H.264/AVC Video Codec","authors":"DaeOk Kim, E. Jung, Hyunho Park, Hosoon Shin, D. Har","doi":"10.1109/IWSOC.2006.348257","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348257","url":null,"abstract":"Context-based adaptive variable length coding (CAVLC) is entropy coding for H.264/AVC video codec. Since the CAVLC is highly context-adaptive and of a block-based context formation, high coding efficiency is achieved. However, its high complexity causes various difficulties in full-hardware implementation. This paper presents high performance hardware architecture of CAVLC. The proposed architecture is implemented in a FPGA device, and verified by RTL simulations. The implementation results show that the proposed architecture encodes a 4times4 block per 16 clock cycles, and achieves a real-time processing for 1920times1088 frame size with 30-fps video at 100MHz clock speed","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129737488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348235
S. Veeramachaneni, L. Avinash, R. M, M. Srinivas
In this paper, the design of a binary to residue converter architecture based on {2k-1, 2k 2k+l} modulo set is presented. New highly-parallel schemes using (p,2) compressors are described for computing the integer modulo operation (X mod m), where m is restricted to the values 2kplusmn1, for any value of k>1 and X is a 16-bit or a 32-bit number For efficient design, novel 3-2, 4-2 and 5-2 compressors are illustrated and are used as the basic building blocks for the proposed converter designs. The resulting circuits are compared, both qualitatively and quantitatively, in standard CMOS cell technology, with the existing circuits. The results show that the proposed architectures are faster and use lesser hardware than similar circuits known making them a viable option for efficient design
本文提出了一种基于{2k- 1,2k 2k+l}模集的二值到残数转换器的结构设计。描述了使用(p,2)压缩器计算整数模运算(X mod m)的新的高度并行方案，其中m被限制为值2kplusmn1，对于k>的任何值，1和X是16位或32位数字。为了有效的设计，新的3-2,4-2和5-2压缩器被说明，并被用作提议的转换器设计的基本构建块。在标准CMOS电池技术中，所得到的电路与现有电路进行了定性和定量的比较。结果表明，所提出的架构比已知的类似电路更快，使用更少的硬件，使其成为高效设计的可行选择
{"title":"Efficient Modulo (2k±1) Binary to Residue Converters","authors":"S. Veeramachaneni, L. Avinash, R. M, M. Srinivas","doi":"10.1109/IWSOC.2006.348235","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348235","url":null,"abstract":"In this paper, the design of a binary to residue converter architecture based on {2k-1, 2k 2k+l} modulo set is presented. New highly-parallel schemes using (p,2) compressors are described for computing the integer modulo operation (X mod m), where m is restricted to the values 2kplusmn1, for any value of k>1 and X is a 16-bit or a 32-bit number For efficient design, novel 3-2, 4-2 and 5-2 compressors are illustrated and are used as the basic building blocks for the proposed converter designs. The resulting circuits are compared, both qualitatively and quantitatively, in standard CMOS cell technology, with the existing circuits. The results show that the proposed architectures are faster and use lesser hardware than similar circuits known making them a viable option for efficient design","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127114367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348274
J. Cetin, A. Balasinski
Noise of the power supply voltage can disturb SoC operation by modulating signal frequency of its individual blocks related to their drive current. This disturbance typically results from the complex functions of the SoC combined with their low pin count and current routing not supporting the power demand in the different sections of the die. The pin count, minimized to help take advantage of die area reduction due to technology shrinks calls for fewer power domains resulting in an increase of the current per domain. This, combined with the larger resistance and inductance of the wiring to the target location on the die, due to the increased functionality, gives rise to the DC (IR) and transient (L di/dt) voltage droop, the severity of which increases with every product generation. At the same time, the "hot spots" of power distribution are difficult to identify due to the distributed nature of the power supply current and voltage. In this work, a novel approach to evaluate power domain problems in SoC was proposed, based on a multi-level analysis of the distribution of total die power to help determine what design tools should be engaged and at which complexity level. Starting from the initial criterion i.e., silicon verification, it was recommended that power domain analysis is not required for the domains proven on silicon. It was then shown that the analysis at a rudimentary level is sufficient if adequate static and dynamic power safety margins can be proven. In such analysis, one may need to perform a relatively simple block level assessment to ensure product functionality in a standard package, depending on the line inductance and operating frequency. For the high die current levels, one would be required to use advanced design tools to resolve problems within every current node and voltage loop, and the preliminary analysis can help define the critical domains. How the noise of the power supply system should be considered throughout the design review process was shown
{"title":"A Method to Evaluate Power Domain Problems in SoC","authors":"J. Cetin, A. Balasinski","doi":"10.1109/IWSOC.2006.348274","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348274","url":null,"abstract":"Noise of the power supply voltage can disturb SoC operation by modulating signal frequency of its individual blocks related to their drive current. This disturbance typically results from the complex functions of the SoC combined with their low pin count and current routing not supporting the power demand in the different sections of the die. The pin count, minimized to help take advantage of die area reduction due to technology shrinks calls for fewer power domains resulting in an increase of the current per domain. This, combined with the larger resistance and inductance of the wiring to the target location on the die, due to the increased functionality, gives rise to the DC (IR) and transient (L di/dt) voltage droop, the severity of which increases with every product generation. At the same time, the \"hot spots\" of power distribution are difficult to identify due to the distributed nature of the power supply current and voltage. In this work, a novel approach to evaluate power domain problems in SoC was proposed, based on a multi-level analysis of the distribution of total die power to help determine what design tools should be engaged and at which complexity level. Starting from the initial criterion i.e., silicon verification, it was recommended that power domain analysis is not required for the domains proven on silicon. It was then shown that the analysis at a rudimentary level is sufficient if adequate static and dynamic power safety margins can be proven. In such analysis, one may need to perform a relatively simple block level assessment to ensure product functionality in a standard package, depending on the line inductance and operating frequency. For the high die current levels, one would be required to use advanced design tools to resolve problems within every current node and voltage loop, and the preliminary analysis can help define the critical domains. How the noise of the power supply system should be considered throughout the design review process was shown","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130712744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IWSOC.2006.348237
C. Raghunandan, K. S. Sainarayanan, M. Srinivas
Interconnects dominate system performance in DSM (deep sub-micron) domain. In shrinking technologies, propagation delay of on-chip interconnects is becoming a major concern. The present work tries to combine encoding with repeater insertion to reduce the propagation delay in VLSI interconnects. A new coding algorithm for minimizing delay has been proposed which eliminates the cross talk classes 4, 5 and 6. In addition to it, an attempt has been made to combine the proposed coding scheme with repeater insertion for further delay minimization. To observe the effect of technology on delay minimization, simulations have been carried out at different technological nodes (180, 130, 90 and 65 nm) for different wire lengths (5,10 mm). Experimental results reveal that there is a significant amount of delay reduction because of this coding technique combined with repeater insertion which appears to perform better than existing techniques in literature
{"title":"Encoding with Repeater Insertion for Minimizing Delay in VLSI Interconnects","authors":"C. Raghunandan, K. S. Sainarayanan, M. Srinivas","doi":"10.1109/IWSOC.2006.348237","DOIUrl":"https://doi.org/10.1109/IWSOC.2006.348237","url":null,"abstract":"Interconnects dominate system performance in DSM (deep sub-micron) domain. In shrinking technologies, propagation delay of on-chip interconnects is becoming a major concern. The present work tries to combine encoding with repeater insertion to reduce the propagation delay in VLSI interconnects. A new coding algorithm for minimizing delay has been proposed which eliminates the cross talk classes 4, 5 and 6. In addition to it, an attempt has been made to combine the proposed coding scheme with repeater insertion for further delay minimization. To observe the effect of technology on delay minimization, simulations have been carried out at different technological nodes (180, 130, 90 and 65 nm) for different wire lengths (5,10 mm). Experimental results reveal that there is a significant amount of delay reduction because of this coding technique combined with repeater insertion which appears to perform better than existing techniques in literature","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123180980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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