A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations

Abstract

In this work, we present a reconfigurable SRAM computing-in-memory (CIM) macro supporting ping-pong operation and pipeline operation for multi-mode multiply-and-accumulate (MAC) operations. The macro can be reconfigured to execute AND or XNOR, offering great flexibilities to cover binary neural network (BNN), ternary neural network (TNN), and multi-bit operation through serially 1-bit AND operations. The main contributions include: (1) A reconfigurable scheme to map inputs and weight of 8T1C bit-cell, supporting three MAC operations; (2) An architecture integrated ping-pong operation and two-level CIM pipeline. Simulated in a standard 28-nm process, the proposed design shows good computing linearity and variations. The average energy efficiency of 1b-AND, BNN, and TNN MAC operation are 1533.7, 1522.9, and 1713.2 TOPS/W, respectively.