High power efficient and scalable noise-shaping SAR ADC for IoT sensors

Abstract

A high power efficient and scalable noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. 97.99 dB SNDR and 111.8 dB SFDR for 2 kHz bandwidth with only 37.1 μW power consumption is measured. By increasing sampling frequency, the performance of the ADC is changed to 93.95 dB SNDR and 108.0 SFDR for 20 kHz bandwidth with 493.1 μW power consumption.