M. Bombana, G. Buonanno, P. Cavalloro, D. Sciuto, G. Zaza
{"title":"A multilevel testability assistant for VLSI design","authors":"M. Bombana, G. Buonanno, P. Cavalloro, D. Sciuto, G. Zaza","doi":"10.1109/EURDAC.1992.246234","DOIUrl":null,"url":null,"abstract":"The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246234","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules.<>
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