Stress, Test, and Simulation of Analog IOs on Automotive ICs

Abstract

Automotive ICs (Integrated Circuits) demand extremely high reliability and quality requirements. On the advanced technology nodes to enable autonomous driving with exploding amount of input/output (IO) data, more and more analog IO pads have been implemented on the automotive ICs, which pose a unique challenge on how to effectively and safely stress them to meet automotive Zero Defect (ZD) requirement. In this paper, we present a stress, test and simulation methodology on analog multi-voltage IOs in which the stress conditions are determined by circuit level reliability simulation while silicon stress results are used to correlate to the simulation models. Silicon results on 16nm FinFET automotive microprocessor are discussed to demonstrate the effectiveness of our methodology.