A low-power FPN attenuation method in the double-log PMOS APS

Abstract

The active-pixel-sensor (APS) imagers operating in logarithmic mode yield high-dynamic-range images. However, this pixel exhibits a small output signal voltage swing. The double-log PMOS APS improves the signal swing in a factor higher than two compared with the conventional log APS. Fixed-pattern noise across the focal-plane array is particularly critical in the log mode, but can be reduced by double sampling techniques with a voltage reference. This voltage reference is established by means of an internal current and is subject to higher power consumption. In this work an in-pixel voltage reference in voltage mode is proposed, providing a more efficient control and consuming less power than the previous solution, while preserving five transistors per pixel, as before.