{"title":"A Class E Digital Transmitter for 16-APSK","authors":"G. Watkins","doi":"10.23919/eumc.2018.8541797","DOIUrl":null,"url":null,"abstract":"A digital transmitter architecture is described composed of two independent class E amplifiers with different saturate output powers (POUT). Their output ports are connected directly together without a switch or combiner. The two amplifiers are enabled or disabled by alternatively biasing their gates in synch with the envelope of the input signal. The transmitter is optimised for 16 state amplitude phase shift keying (16-APSK). Under simulation, the two class E amplifiers were optimised for a POUT of 13.6 dBm and 22.7 dBm. 71.4% and 78.2 % power added efficiency (P AE) was achieved respectively. The same transistor was used for both amplifiers and the different POUT defined by the quality factor (Q) of their output bandpass filter (BPF). A practical implementation achieved 49.8% and 45.6% PAE at POUTS of 14.0 dBm and 20.3 dBm respectively. With a 16-APSK signal, 46.9% PAE was achieved at 19.8 dBm POUT, with an error vector magnitude (EVM) of 5.7%.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"62 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/eumc.2018.8541797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A digital transmitter architecture is described composed of two independent class E amplifiers with different saturate output powers (POUT). Their output ports are connected directly together without a switch or combiner. The two amplifiers are enabled or disabled by alternatively biasing their gates in synch with the envelope of the input signal. The transmitter is optimised for 16 state amplitude phase shift keying (16-APSK). Under simulation, the two class E amplifiers were optimised for a POUT of 13.6 dBm and 22.7 dBm. 71.4% and 78.2 % power added efficiency (P AE) was achieved respectively. The same transistor was used for both amplifiers and the different POUT defined by the quality factor (Q) of their output bandpass filter (BPF). A practical implementation achieved 49.8% and 45.6% PAE at POUTS of 14.0 dBm and 20.3 dBm respectively. With a 16-APSK signal, 46.9% PAE was achieved at 19.8 dBm POUT, with an error vector magnitude (EVM) of 5.7%.