Via Size Optimization for Optimum Circuit Performance at 3 nm node

Abstract

Via size and placement for layer-to-layer connection needs careful assessment. Small via size offers compact pitch and denser connections between metal layers, while larger via size offers reduced resistance for better performance. In this paper, an optimization scheme for via size is presented, without changing the density of via allocation. We show that increasing via CD reduces resistance, resulting in enhanced performance. However, this also results in increased capacitance between different circuit nodes, which causes degradation in performance. These two opposite effects result in an optimum via CD, which offers best performance. We also show that this optimum via CD depends on the resistivity of the via material and the dielectric constant of inter-layer dielectric (ILD) surrounding the via. Via design guidelines for TiN/Co via material and for a futuristic barrier-less metal with equivalent resistivity 1/10th} of cobalt via, is presented for different dielectric constants of surrounding dielectrics.