Modeling arbitrator delay-area dependencies in customizable instruction set processors

Abstract

Instruction set customization is becoming a preferred approach for accelerating high-speed demanding applications. In this paper, we present performance and delay-area product estimation models to accelerate the design of custom instructions on the Nios II configurable processor platform. The proposed models outline the performance bandwidth and delay-area product to enable profitable selection on the type and number of custom instructions, without the need to undertake time-consuming hardware synthesis in the design exploration stage. The models exhibit a high degree of accuracy as they incorporate the architectural dependencies of the arbitrator logic between the Nios II processor and custom hardware. Experimental results reveal that the area-time implications of the arbitrator logic with respect to the number of custom instructions can significantly affect the system's performance and area utilization.