A novel memory bus driver/receiver architecture for higher throughput

Abstract

A high-speed memory bus interface which enables greater throughput for data reads and writes is described in this paper. Current mode CMOS logic synthesis methods are used to implement multi-valued logic (MVL) functions to create a high bandwidth bus. First, a fundamental bi-directional data bus for multiple logic levels is presented. Then a bi-directional data bus with impedance matching terminators is presented. Finally a novel Adaptive Multi-Level Simultaneous bi-directional Transceiver (AMLST) bus structure for cache or main memory is proposed. The proposed bus can balance the memory channel bandwidth with the instruction execution rate of modern processors. Despite the problems encountered in implementing complete systems with MVL circuits, among which are circuit speed and design automation support, there is great potential in the future for this approach.