{"title":"Impact of diameter on TFET conduction mechanisms","authors":"V. B. Sivieri, P. Agopian, J. Martino","doi":"10.1109/SBMICRO.2015.7298146","DOIUrl":null,"url":null,"abstract":"In this work, the impact of diameter on the TFET conduction mechanisms and the consequent influence on the device performance is investigated through simulation analysis. The results show a higher current level and a lower gate voltage to reach the band-to-band tunneling regime in NW-TFETs with smaller diameters. Some anomalies related to the performance degradation were found in the transfer characteristic curves of the narrower devices (D <; 30 nm) and are analyzed based on the simulated energy band diagrams and tunneling rate values. The Si NW-TFET with 10 nm diameter presented a drain current approximately 3 orders of magnitude lower than the larger nanowires at high gate voltages due to presence of gate/source overlap region in abrupt source/channel junction.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"347 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMICRO.2015.7298146","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this work, the impact of diameter on the TFET conduction mechanisms and the consequent influence on the device performance is investigated through simulation analysis. The results show a higher current level and a lower gate voltage to reach the band-to-band tunneling regime in NW-TFETs with smaller diameters. Some anomalies related to the performance degradation were found in the transfer characteristic curves of the narrower devices (D <; 30 nm) and are analyzed based on the simulated energy band diagrams and tunneling rate values. The Si NW-TFET with 10 nm diameter presented a drain current approximately 3 orders of magnitude lower than the larger nanowires at high gate voltages due to presence of gate/source overlap region in abrupt source/channel junction.