Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298115
A. R. Leite, R. R. Lima, E. Simões, M. L. P. Silva
The aim of this work was to simulate, produce and tests a small-lab that possesses an array of miniaturized 3D structures with four different unit operations. These structures showed to be useful for particle removal and pre-concentration in sample pre-treatment in Chemical analysis or mixing and spray formation in Chemical Engineering synthesis. The device proposed showed to be a versatile and low-cost system that can be built using conventional tools.
{"title":"Array of miniaturized structures applied to small-labs development","authors":"A. R. Leite, R. R. Lima, E. Simões, M. L. P. Silva","doi":"10.1109/SBMICRO.2015.7298115","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298115","url":null,"abstract":"The aim of this work was to simulate, produce and tests a small-lab that possesses an array of miniaturized 3D structures with four different unit operations. These structures showed to be useful for particle removal and pre-concentration in sample pre-treatment in Chemical analysis or mixing and spray formation in Chemical Engineering synthesis. The device proposed showed to be a versatile and low-cost system that can be built using conventional tools.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125481853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298127
Fabiano A. Colling, C. Moraes, Celso Peter, E. Rhod, W. Hasenkamp, Dong-Hyun Park, T. Oh
The Package on Package (PoP) emerges as a package alternative to increase the number of transistors in the same area by stacking thin chips. The differences in thermal and mechanical properties of the various materials that constitute the encapsulated chip can result in the device warpage. In this study the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. The factors that contribute to generate warping in semiconductor encapsulated with PoP technology during the solder reflow process were evaluated. This study evaluates the conditions and process parameters during fabrication of a 40 μm thick chip molded with one kind of Epoxy Molding Compound (EMC). Through the warpage measurements by Moire interferometry it was possible to build correlations with computer simulation of the device. The results of this comparison were used as a basis for simulation and validation of input data used in other settings for three different thicknesses of silicon chips (40, 100 and 200 microns) and two different types of EMC (EMC1 and EMC2). In the simulations, it was found the warpage of the 40 microns thick chips, considering the different epoxy compounds, decreased by about 40% in the top chip, the reduction obtained in the 100 microns thick chips was in the order of 35%, while in the 200 microns thick chips the warpage decreased by about 3%. The results show the importance of simulation to predict the tendency of warping when there are variations in the fabrication process parameters.
{"title":"Numerical evaluation of warpage in PoP encapsulated semiconductors","authors":"Fabiano A. Colling, C. Moraes, Celso Peter, E. Rhod, W. Hasenkamp, Dong-Hyun Park, T. Oh","doi":"10.1109/SBMICRO.2015.7298127","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298127","url":null,"abstract":"The Package on Package (PoP) emerges as a package alternative to increase the number of transistors in the same area by stacking thin chips. The differences in thermal and mechanical properties of the various materials that constitute the encapsulated chip can result in the device warpage. In this study the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. The factors that contribute to generate warping in semiconductor encapsulated with PoP technology during the solder reflow process were evaluated. This study evaluates the conditions and process parameters during fabrication of a 40 μm thick chip molded with one kind of Epoxy Molding Compound (EMC). Through the warpage measurements by Moire interferometry it was possible to build correlations with computer simulation of the device. The results of this comparison were used as a basis for simulation and validation of input data used in other settings for three different thicknesses of silicon chips (40, 100 and 200 microns) and two different types of EMC (EMC1 and EMC2). In the simulations, it was found the warpage of the 40 microns thick chips, considering the different epoxy compounds, decreased by about 40% in the top chip, the reduction obtained in the 100 microns thick chips was in the order of 35%, while in the 200 microns thick chips the warpage decreased by about 3%. The results show the importance of simulation to predict the tendency of warping when there are variations in the fabrication process parameters.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298113
A. R. Molto, R. T. Doria, M. de Souza, M. Pavanello
This paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.
{"title":"On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs","authors":"A. R. Molto, R. T. Doria, M. de Souza, M. Pavanello","doi":"10.1109/SBMICRO.2015.7298113","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298113","url":null,"abstract":"This paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298154
A. Alaferdov, R. Savu, S. Račkauskas, T. Rackauskas, M. A. Canesqui, Y. A. Gromova, Anna O. Orlova, Alexander V. Baranov, A. Fedorov, S. Moshkalev
Fabrication of novel micron-scale structures based on multi-layer graphene and quantum dots (QD) hybrids is presented. Two types of CdSe/ZnS (core/shell) QDs with diameters of 5.3 and 2.5 nm and photoluminescence peaks at 630 and 530 nm, respectively, were used. The photoresponse for illumination by a 473 nm wavelength laser was found to change polarity for these two types of QDs, being positive for larger and negative to smaller ones. The presented photo-resistive devices can be used for studies of the mechanisms responsible for photoinduced change of graphene layer conductivity in presence of QDs.
{"title":"New hybrid structures based on CdSe/ZnS quantum dots and multilayer graphene for photonics applications","authors":"A. Alaferdov, R. Savu, S. Račkauskas, T. Rackauskas, M. A. Canesqui, Y. A. Gromova, Anna O. Orlova, Alexander V. Baranov, A. Fedorov, S. Moshkalev","doi":"10.1109/SBMICRO.2015.7298154","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298154","url":null,"abstract":"Fabrication of novel micron-scale structures based on multi-layer graphene and quantum dots (QD) hybrids is presented. Two types of CdSe/ZnS (core/shell) QDs with diameters of 5.3 and 2.5 nm and photoluminescence peaks at 630 and 530 nm, respectively, were used. The photoresponse for illumination by a 473 nm wavelength laser was found to change polarity for these two types of QDs, being positive for larger and negative to smaller ones. The presented photo-resistive devices can be used for studies of the mechanisms responsible for photoinduced change of graphene layer conductivity in presence of QDs.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298118
A. Oliveira, P. Agopian, J. Martino, E. Simoen, C. Claeys, H. Mertens, N. Collaert, A. Thean
This paper presents for the first time an experimental analysis of germanium pMOSFETs operating in conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes. In addition, there are two different HfO2/Al2O3 gate stack thicknesses under evaluation. The subthreshold swing (SS) improves 60% in eDT (k = 2) mode compared to the conventional mode (k = 0) thanks to the dynamic threshold voltage reduction. The thinnest Al2O3 layer presents higher drain current hysteresis in the conventional mode and it increases when the channel length decreases. In contrast, the hysteresis effect reduces from 67 mV to lower than 4 mV, i.e. practically minimized when the dynamic threshold voltage is applied.
{"title":"Dynamic threshold voltage influence on Ge pMOSFET hysteresis","authors":"A. Oliveira, P. Agopian, J. Martino, E. Simoen, C. Claeys, H. Mertens, N. Collaert, A. Thean","doi":"10.1109/SBMICRO.2015.7298118","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298118","url":null,"abstract":"This paper presents for the first time an experimental analysis of germanium pMOSFETs operating in conventional, dynamic threshold voltage (DT, where V<sub>BS</sub> = V<sub>GS</sub>) and enhanced dynamic threshold voltage (eDT, where V<sub>BS</sub>=k*V<sub>GS</sub>) modes. In addition, there are two different HfO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> gate stack thicknesses under evaluation. The subthreshold swing (SS) improves 60% in eDT (k = 2) mode compared to the conventional mode (k = 0) thanks to the dynamic threshold voltage reduction. The thinnest Al<sub>2</sub>O<sub>3</sub> layer presents higher drain current hysteresis in the conventional mode and it increases when the channel length decreases. In contrast, the hysteresis effect reduces from 67 mV to lower than 4 mV, i.e. practically minimized when the dynamic threshold voltage is applied.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127293976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298150
L. P. Pedraza Caballero, J. P. Vasco, P. Guimarães, Omar P. Vilela Neto
In this paper we propose, for the first time, all-optical Majority and Feynman gates in two-dimensional silicon photonic crystals. Photonic crystals are optical semiconductor nanodevices, formed by a periodicity in one, two or three dimensions in the refractive index of a macroscopic media. These devices can operate with low power consumption, high speed and low dissipation of energy to heat. A photonic crystal waveguide is a perfect platform to accomplish the design of all-optical devices. The functionality of logic gates proposed here is achieved due to the light beam interference effect. For the Majority gate, the simulation results show that the transmission to define logic 0 is less than 35% and logic 1 greater than 85%. In addition, for the Feynman gate the transmission to define logic 0 and logic 1 are ≤10% and ≥ 40%, respectively. In order to perform the simulations we applied the FDTD method in the MEEP software package. The Majority and Feynman logic devices presented here can be potential candidates for the realization of low power photonic computational circuits.
{"title":"All-optical Majority and Feynman gates in photonic crystals","authors":"L. P. Pedraza Caballero, J. P. Vasco, P. Guimarães, Omar P. Vilela Neto","doi":"10.1109/SBMICRO.2015.7298150","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298150","url":null,"abstract":"In this paper we propose, for the first time, all-optical Majority and Feynman gates in two-dimensional silicon photonic crystals. Photonic crystals are optical semiconductor nanodevices, formed by a periodicity in one, two or three dimensions in the refractive index of a macroscopic media. These devices can operate with low power consumption, high speed and low dissipation of energy to heat. A photonic crystal waveguide is a perfect platform to accomplish the design of all-optical devices. The functionality of logic gates proposed here is achieved due to the light beam interference effect. For the Majority gate, the simulation results show that the transmission to define logic 0 is less than 35% and logic 1 greater than 85%. In addition, for the Feynman gate the transmission to define logic 0 and logic 1 are ≤10% and ≥ 40%, respectively. In order to perform the simulations we applied the FDTD method in the MEEP software package. The Majority and Feynman logic devices presented here can be potential candidates for the realization of low power photonic computational circuits.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298153
D. Micha, E. Weiner, R. Jakomin, R. Kawabata, R. Mourão, M. Pires, P. L. Souza
Quantum dot intermediate band solar cells (QD-IBSC) have been produced in order to pave the road to high efficiency solar cells, demonstrating sub-bandgap absorption. Even though the obtained figures of merit are still lower than those of the samples without the quantum dots, optical activity of the nanostructures has been demonstrated. While the photovoltaic activity of the QD-IBSC is observed for wavelengths until 1000 nm, it vanishes at around 900 nm for the reference sample. We conclude that improvement in the QD morphological structure is still needed to minimize surface recombination and that more layers and a higher QD density is mandatory to increase the overall sub-bandgap absorption. Finally, a potential change in the solar cell growth conditions is suggested.
{"title":"InAs quantum dots on GaAs for intermediate band solar cells","authors":"D. Micha, E. Weiner, R. Jakomin, R. Kawabata, R. Mourão, M. Pires, P. L. Souza","doi":"10.1109/SBMICRO.2015.7298153","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298153","url":null,"abstract":"Quantum dot intermediate band solar cells (QD-IBSC) have been produced in order to pave the road to high efficiency solar cells, demonstrating sub-bandgap absorption. Even though the obtained figures of merit are still lower than those of the samples without the quantum dots, optical activity of the nanostructures has been demonstrated. While the photovoltaic activity of the QD-IBSC is observed for wavelengths until 1000 nm, it vanishes at around 900 nm for the reference sample. We conclude that improvement in the QD morphological structure is still needed to minimize surface recombination and that more layers and a higher QD density is mandatory to increase the overall sub-bandgap absorption. Finally, a potential change in the solar cell growth conditions is suggested.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115094380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298130
I. Hernández, M. Estrada, I. Garduño, J. Tinoco, A. Cerdeira
The electrical properties of RF magnetron sputtered HfO2 layers as dielectric and Hafnium-Indium-Zinc-Oxide HIZO as semiconductor in metal-insulator-semiconductor (MIS) structures are investigated. The dielectric constant of the HfO2 layer was around 9 measured at 10 kHz. The critical electric field was higher than 5×105 V/cm and the leakage current below 5×10-9 A/cm2. The effective charged density of interface states in the order of 5×1012 cm-2. Flat band shift due to polarization of the dielectric at voltage rage between -5 and 5 V is below 0.5 V. The RF deposited HIZO layer presents higher density of interface and bulk traps than similar layers deposited by other more complex techniques requiring higher processing temperature. However, results indicate that they can still be used in low voltage range amorphous oxide semiconductor thin film transistors AOSTFTs.
{"title":"Characterization of HfO2 on Hafnium-Indium-Zinc Oxide HIZO layer metal-insulator-semiconductor structures deposited by RF sputtering","authors":"I. Hernández, M. Estrada, I. Garduño, J. Tinoco, A. Cerdeira","doi":"10.1109/SBMICRO.2015.7298130","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298130","url":null,"abstract":"The electrical properties of RF magnetron sputtered HfO<sub>2</sub> layers as dielectric and Hafnium-Indium-Zinc-Oxide HIZO as semiconductor in metal-insulator-semiconductor (MIS) structures are investigated. The dielectric constant of the HfO<sub>2</sub> layer was around 9 measured at 10 kHz. The critical electric field was higher than 5×10<sup>5</sup> V/cm and the leakage current below 5×10<sup>-9</sup> A/cm<sup>2</sup>. The effective charged density of interface states in the order of 5×10<sup>12</sup> cm<sup>-2</sup>. Flat band shift due to polarization of the dielectric at voltage rage between -5 and 5 V is below 0.5 V. The RF deposited HIZO layer presents higher density of interface and bulk traps than similar layers deposited by other more complex techniques requiring higher processing temperature. However, results indicate that they can still be used in low voltage range amorphous oxide semiconductor thin film transistors AOSTFTs.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298122
Marcello Marcelino Correia, S. Gimenez
Through three-dimensional numerical simulations, we investigate the use of ellipsoidal layout style on the electrical performance of a Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) switch. This gate geometry is capable to adding two new effects in the MOSFET structure named Longitudinal Corner Effect (LCE) and Parallel Connection of MOSFET with Different Channel Lengths Effect (PAMDLE) that result in the boosting of the main digital figures of merit. The main findings of this work demonstrate that the Ellipsoidal gate geometry is a viable alternative layout style to implement MOSFET switches to significantly improve its electrical performance and, consequently, the performance of the DC/DC converters.
{"title":"Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style","authors":"Marcello Marcelino Correia, S. Gimenez","doi":"10.1109/SBMICRO.2015.7298122","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298122","url":null,"abstract":"Through three-dimensional numerical simulations, we investigate the use of ellipsoidal layout style on the electrical performance of a Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) switch. This gate geometry is capable to adding two new effects in the MOSFET structure named Longitudinal Corner Effect (LCE) and Parallel Connection of MOSFET with Different Channel Lengths Effect (PAMDLE) that result in the boosting of the main digital figures of merit. The main findings of this work demonstrate that the Ellipsoidal gate geometry is a viable alternative layout style to implement MOSFET switches to significantly improve its electrical performance and, consequently, the performance of the DC/DC converters.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117335670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-15DOI: 10.1109/SBMICRO.2015.7298151
A. L. F. Cauduro, C. I. Sombrio, P. Franzen, H. Boudinov, D. L. Baptista
Optical properties of ZnO nanowires were investigated through photoluminescence (PL) at room and low temperatures. An excitonic structure was observed in the UV band emission and we are able to distinguish between free excitons, bound excitons and donor acceptor pairs. The PL spectra shows deep level emissions ranging from 1.4 eV up to 2.8 eV, strongly depending on surface defects whereas the red emission (1.7 eV) is activated at cryogenic temperatures. We attribute the green luminescence (2.4 eV) emission to the presence of zinc vacancies into ZnO nanowires. Further evidences that confirm the mechanism are observed in the PL emission spectra after annealing in O2 or Ar environments.
{"title":"Engineering of the photoluminescence of ZnO nanowires by different growth and annealing environments","authors":"A. L. F. Cauduro, C. I. Sombrio, P. Franzen, H. Boudinov, D. L. Baptista","doi":"10.1109/SBMICRO.2015.7298151","DOIUrl":"https://doi.org/10.1109/SBMICRO.2015.7298151","url":null,"abstract":"Optical properties of ZnO nanowires were investigated through photoluminescence (PL) at room and low temperatures. An excitonic structure was observed in the UV band emission and we are able to distinguish between free excitons, bound excitons and donor acceptor pairs. The PL spectra shows deep level emissions ranging from 1.4 eV up to 2.8 eV, strongly depending on surface defects whereas the red emission (1.7 eV) is activated at cryogenic temperatures. We attribute the green luminescence (2.4 eV) emission to the presence of zinc vacancies into ZnO nanowires. Further evidences that confirm the mechanism are observed in the PL emission spectra after annealing in O2 or Ar environments.","PeriodicalId":342493,"journal":{"name":"2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124246512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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