T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, H. T. Vergos
{"title":"A class of easily path delay fault testable circuits","authors":"T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, H. T. Vergos","doi":"10.1109/SSMSD.2000.836466","DOIUrl":null,"url":null,"abstract":"The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.","PeriodicalId":166604,"journal":{"name":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSMSD.2000.836466","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.
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