Formal Description of Possible Input Logical Signal Data Sequences for Digital Systems and Their Blocks

Abstract

Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.