Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524733
J. Podivínský, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek
A processor plays the main role in almost every electronic system. The use of a general purpose processor may not be suitable for a specific application, because the processor is designed for a wide set of applications. The Application-Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where a single application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking the possible configurations of its key parameters (such as the number of registers, cache sizes, instruction set modifications, etc.). The paper also presents a designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modeling and evaluation, the Codasip Studio tool is used. It allows to generate all the tools necessary for compilation, simulation, and hardware mapping which are used in the process of the ASIP design. The experiments are carried out on a RISC- V (Reduced Instruction Set Computing) processor.
处理器几乎在每一个电子系统中都起着主要作用。通用处理器的使用可能不适合特定的应用程序，因为处理器是为广泛的应用程序设计的。应用程序专用指令集处理器(application - specific Instruction-set Processors, asip)目前应用于特定的情况，即执行单个应用程序或特定的一组应用程序。本文的重点是通过检查其关键参数(如寄存器数量、缓存大小、指令集修改等)的可能配置，对给定应用程序的ASIP进行自动优化。本文还提出了一个设计框架，能够在速度，面积或功耗方面优化给定的应用。该框架允许使用各种优化方法。对于处理器建模和评估，使用Codasip Studio工具。它允许生成在ASIP设计过程中使用的编译、仿真和硬件映射所需的所有工具。实验在RISC- V(精简指令集计算)处理器上进行。
{"title":"A Processor Optimization Framework for a Selected Application","authors":"J. Podivínský, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek","doi":"10.1109/EWDTS.2018.8524733","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524733","url":null,"abstract":"A processor plays the main role in almost every electronic system. The use of a general purpose processor may not be suitable for a specific application, because the processor is designed for a wide set of applications. The Application-Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where a single application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking the possible configurations of its key parameters (such as the number of registers, cache sizes, instruction set modifications, etc.). The paper also presents a designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modeling and evaluation, the Codasip Studio tool is used. It allows to generate all the tools necessary for compilation, simulation, and hardware mapping which are used in the process of the ASIP design. The experiments are carried out on a RISC- V (Reduced Instruction Set Computing) processor.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115401174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524647
N. Goncharova
The article analyzes the current state and perspectives of the development of automated systems of the vehicle input flow operation at multimodal terminal complexes in Russia. Fed-batch technologies of vehicles supply to the terminal are considered as a way of increasing the terminal process's rhythmicity. Time-slotting smooths out unevenness by redistributing the delivery of transport over the working shifts of the terminal. The use of this logistics technology allows avoiding queues at the terminal and makes it possible to service all incoming applications in the specified period while preserving possible profit. The algorithm of time-slotting technology application in terminal complexes is considered.
{"title":"The Development of Automated Systems of the Vehicle Input Flow Operation at Multimodal Terminal Complexes as a Way to Increase the Terminal Process's Rhythmicity","authors":"N. Goncharova","doi":"10.1109/EWDTS.2018.8524647","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524647","url":null,"abstract":"The article analyzes the current state and perspectives of the development of automated systems of the vehicle input flow operation at multimodal terminal complexes in Russia. Fed-batch technologies of vehicles supply to the terminal are considered as a way of increasing the terminal process's rhythmicity. Time-slotting smooths out unevenness by redistributing the delivery of transport over the working shifts of the terminal. The use of this logistics technology allows avoiding queues at the terminal and makes it possible to service all incoming applications in the specified period while preserving possible profit. The algorithm of time-slotting technology application in terminal complexes is considered.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116673811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524753
V. Zakharov, S. Shalagin, B. F. Eminov
This paper considers a pseudo-random sequence generator in form of a autonomous automaton with the output function. A model of the automaton output function is proposed, which is defined based on a set of invertible matrices, with the capacity relevant to the maximum number of the bijective transformations of two binary variables over the GF(2) field. In the model proposed, there is an algorithmic possibility to modify the structure of pseudo-random sequences read on the automaton output, as related to the input M-sequence within the period equal to 2n-1, n > 1. The output function of a given automaton allows obtaining an assembly of output sequences, which is defined by the lower estimate written as O(22n). Based on the model proposed, a pseudo-random sequence generator hardware implementation is presented, with the period of 2n-1, n = 256, in the FPGA basis, using the Xilinx ISE WebPACK 14.7 CAD software product. Hardware complexity estimates of the generator are presented, as well. It is shown that the hardware complexity relating to the pseudo-random sequence generator implementation, which are represented in the FPGA XC3 S700A basis, increase linearly with the increase of n.
本文考虑了一个具有输出函数的自治自动机形式的伪随机序列发生器。提出了自动机输出函数的一个模型，该模型基于一组可逆矩阵来定义，其容量与两个二元变量在GF(2)域上的双射变换的最大次数有关。在所提出的模型中，存在一种算法可能性，可以修改自动机输出上读取的伪随机序列的结构，与输入m序列在等于2n-1, n > 1的周期内相关。给定自动机的输出函数允许获得输出序列的集合，该集合由写为O(22n)的较低估计值定义。基于所提出的模型，利用Xilinx ISE WebPACK 14.7 CAD软件产品，在FPGA基础上实现了周期为2n-1, n = 256的伪随机序列发生器的硬件实现。同时给出了该发生器的硬件复杂度估计。结果表明，在FPGA XC3 S700A基上表示的伪随机序列发生器实现的硬件复杂度随着n的增加呈线性增加。
{"title":"Model and FPGA Implementation of Pseudorandom Sequence Generators Based on Invertible Matrices","authors":"V. Zakharov, S. Shalagin, B. F. Eminov","doi":"10.1109/EWDTS.2018.8524753","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524753","url":null,"abstract":"This paper considers a pseudo-random sequence generator in form of a autonomous automaton with the output function. A model of the automaton output function is proposed, which is defined based on a set of invertible matrices, with the capacity relevant to the maximum number of the bijective transformations of two binary variables over the GF(2) field. In the model proposed, there is an algorithmic possibility to modify the structure of pseudo-random sequences read on the automaton output, as related to the input M-sequence within the period equal to 2n-1, n > 1. The output function of a given automaton allows obtaining an assembly of output sequences, which is defined by the lower estimate written as O(22n). Based on the model proposed, a pseudo-random sequence generator hardware implementation is presented, with the period of 2n-1, n = 256, in the FPGA basis, using the Xilinx ISE WebPACK 14.7 CAD software product. Hardware complexity estimates of the generator are presented, as well. It is shown that the hardware complexity relating to the pseudo-random sequence generator implementation, which are represented in the FPGA XC3 S700A basis, increase linearly with the increase of n.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524722
Anton Bliudov, I. Nazarov, V. Dmitriev, Konstantin Kovalyov
This paper describes the algorithm of formationof new code with weight-based summation. Authors prove that this code detect all single and twofold distortions in data bits. Also other properties of this code considering hardware and information redundancy are stated. The main attention is paid to the ability of this code to detect 100% of single errors in the tested circuit with relatively low redundancy and analysis of structure of its errors that allow to reach this goal. Results are verified by the experiments using the set of LGSynth '89 benchmarks.
{"title":"Use of Systematic Code Based on Data Bits Weighing for Concurrent Error Detection Considering Error Structure Analysis","authors":"Anton Bliudov, I. Nazarov, V. Dmitriev, Konstantin Kovalyov","doi":"10.1109/EWDTS.2018.8524722","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524722","url":null,"abstract":"This paper describes the algorithm of formationof new code with weight-based summation. Authors prove that this code detect all single and twofold distortions in data bits. Also other properties of this code considering hardware and information redundancy are stated. The main attention is paid to the ability of this code to detect 100% of single errors in the tested circuit with relatively low redundancy and analysis of structure of its errors that allow to reach this goal. Results are verified by the experiments using the set of LGSynth '89 benchmarks.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127257197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524649
I. Makarova, P. Buyvol, K. Shubenkova, E. Tsybunov, A. Boyko
The growth of urbanization, which mobility demand increases, leads to an growth in the transport complex's negative impact on the environment. This causes the urgency focused of “green” types of transport, such as a bicycle. The growing popularity of this transport type throughout the world is due to its low cost and environmental friendliness. To expand the potential cyclists, range, we offer the smart bike concept that will help an untrained cyclist in situations where health, as well as environmental parameters, create difficulties for the trip. The concept of bicycle management, as well as the algorithm for identifying the current state of the system, based on the neural networks, are described.
{"title":"Development of Intelligent Smart Bicycle Control System","authors":"I. Makarova, P. Buyvol, K. Shubenkova, E. Tsybunov, A. Boyko","doi":"10.1109/EWDTS.2018.8524649","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524649","url":null,"abstract":"The growth of urbanization, which mobility demand increases, leads to an growth in the transport complex's negative impact on the environment. This causes the urgency focused of “green” types of transport, such as a bicycle. The growing popularity of this transport type throughout the world is due to its low cost and environmental friendliness. To expand the potential cyclists, range, we offer the smart bike concept that will help an untrained cyclist in situations where health, as well as environmental parameters, create difficulties for the trip. The concept of bicycle management, as well as the algorithm for identifying the current state of the system, based on the neural networks, are described.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"103 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524675
A. Ivannikov, N. Levchenko, I. Romanova
Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.
{"title":"Formal Description of Possible Input Logical Signal Data Sequences for Digital Systems and Their Blocks","authors":"A. Ivannikov, N. Levchenko, I. Romanova","doi":"10.1109/EWDTS.2018.8524675","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524675","url":null,"abstract":"Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"482 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116531886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524868
V. M. Artyushenko, V. I. Volovach
Reviewed and analyzed the issues linked with the moment and cumulant description of non-Gaussian random processes. It is shown that if non-Gaussian random processes are given by both moment and cumulant functions, it is assumed that such processes are completely given. The spectral characteristics of non-Gaussian random processes are considered. It is shown that higher spectral densities exist only for non-Gaussian random processes.
{"title":"Analysis of Moment and Cumulant Description of non-Gaussian Random Processes, Signals and Noise","authors":"V. M. Artyushenko, V. I. Volovach","doi":"10.1109/EWDTS.2018.8524868","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524868","url":null,"abstract":"Reviewed and analyzed the issues linked with the moment and cumulant description of non-Gaussian random processes. It is shown that if non-Gaussian random processes are given by both moment and cumulant functions, it is assumed that such processes are completely given. The spectral characteristics of non-Gaussian random processes are considered. It is shown that higher spectral densities exist only for non-Gaussian random processes.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524853
D. Sargsyan
The safety and reliability requirements for automotive SoCs are becoming stronger requiring more complex and flexible solutions. Hardware implementation of test algorithms in memory built-in self-test (BIST) scheme allows in-field testing only with predefined instructions which restricts flexibility of system test in mission mode. In this paper, firmware generation architecture for memory BIST is described which allows to control mission mode access to embedded memories and makes the in-field testing more flexible.
{"title":"Firmware Generation Architecture for Memory BIST","authors":"D. Sargsyan","doi":"10.1109/EWDTS.2018.8524853","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524853","url":null,"abstract":"The safety and reliability requirements for automotive SoCs are becoming stronger requiring more complex and flexible solutions. Hardware implementation of test algorithms in memory built-in self-test (BIST) scheme allows in-field testing only with predefined instructions which restricts flexibility of system test in mission mode. In this paper, firmware generation architecture for memory BIST is described which allows to control mission mode access to embedded memories and makes the in-field testing more flexible.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122555013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524641
Ondrej Cekan, R. Panek, Z. Kotásek
The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.
{"title":"Input and Output Generation for the Verification of ALU: A Use Case","authors":"Ondrej Cekan, R. Panek, Z. Kotásek","doi":"10.1109/EWDTS.2018.8524641","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524641","url":null,"abstract":"The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124215608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524719
Alexey Malyshev, I. Malay, L. Selin
The article describes a method of Error Vector Magnitude (EVM) measurement based on signal digital processing. Perspective methods of measurement with tracking against standards of SI-system main units is presented. In order to reduce the error of EVM measurement, the article considers the EVM method using a digital oscilloscope. Calculated absolute error of the measurement method is 0.1%. This is much less than common error values of EVM measuring tools.
{"title":"Methods of EVM Measurement and Calibration Algorithms for Measuring Instruments","authors":"Alexey Malyshev, I. Malay, L. Selin","doi":"10.1109/EWDTS.2018.8524719","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524719","url":null,"abstract":"The article describes a method of Error Vector Magnitude (EVM) measurement based on signal digital processing. Perspective methods of measurement with tracking against standards of SI-system main units is presented. In order to reduce the error of EVM measurement, the article considers the EVM method using a digital oscilloscope. Calculated absolute error of the measurement method is 0.1%. This is much less than common error values of EVM measuring tools.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114063659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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