S. Pinel, J. Tasselli, A. Marty, J. Bailbé, E. Beyne, R. Van Hoof, S. Marco, S. Leseduarte, O. Vendier, A. Coello-Vera
{"title":"New ultrathin 3D integration technique: technological and thermal investigations","authors":"S. Pinel, J. Tasselli, A. Marty, J. Bailbé, E. Beyne, R. Van Hoof, S. Marco, S. Leseduarte, O. Vendier, A. Coello-Vera","doi":"10.1117/12.382262","DOIUrl":null,"url":null,"abstract":"A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.","PeriodicalId":318748,"journal":{"name":"Design, Test, Integration, and Packaging of MEMS/MOEMS","volume":"58 20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Design, Test, Integration, and Packaging of MEMS/MOEMS","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.382262","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.
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