Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA

Abstract

Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.