A study of source/drain-on-insulator structure for extremely scaled MOSFETs

Abstract

As MOSFET feature sizes are scaled to the deep sub-0.1 /spl mu/m regime, ultra-shallow source/drain extensions and heavily doped halos are required to suppress short-channel effects. These structures result in high series resistance and parasitic capacitance. A source/drain-on-insulator (SDOI) structure with elevated source/drain combined with an oxide isolation, formed by a shallow trench process underneath the source/drain region, is reported to be a potential solution to simultaneously reduce the series resistance and parasitic capacitance. However, the optimization of SDOI structures is very tricky and the tradeoff between series resistance and gate-to-drain Miller capacitance is not obvious. In this paper, the advantage of this MOSFET source/drain engineered structure is verified by detailed device simulation with extremely scaled MOSFETs. Device structure parameter optimizations are discussed to maximize the intrinsic performance. Design guidelines and potential performance gain with the SDOI structure are also discussed.