Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367802
J. Sim, B. Lee, R. Choi, K. Matthews, D. Kwong, L. Larson, P. Tsui, G. Bersuker
High-k dielectrics have been proposed to replace SiO/sub 2/ to reduce gate leakage current. Among reliability concerns of the hafnium based metal oxides (Y.H. Kim et al., Tech. Dig. of IEDM, p. 861, 2002) hot carrier effects may represent one of the major limitations for the high-k gate dielectrics introduction (Q. Lu et al., IRPS, p.429, 2002; A. Kumar, VLSI, p. 152, 2003). However, most of the studies did not take into consideration that the hot carriers-induced degradation might be accompanied by the electron trapping in the bulk of the high-k film (C.D. Young et al., IRW, p. 28, 2003) due to the high density of structural defects in the high-k dielectrics (G. Bersuker et al., Materials Today, vol. 26, Jan. 2004). This bulk electron trapping, which is not observed in the case of SiO/sub 2/ dielectrics, can significantly affect transistor parameters and, therefore, complicates evaluation of hot carrier degradation properties of the high-k gate stacks. In this paper, we investigate test conditions for the hot carrier stress of the poly and TiN gate NMOSFETs with HfSiON gate dielectric that would more accurately address the above issues.
提出用高k介电体代替SiO/sub /以降低栅漏电流。在铪基金属氧化物的可靠性问题中(Y.H. Kim etal .， Tech. Dig.)。IEDM, p. 861, 2002)热载子效应可能是引入高k栅极电介质的主要限制之一(Q. Lu et al.， IRPS, p.429, 2002;A. Kumar, VLSI，第152页，2003年)。然而，大多数研究都没有考虑到，由于高k介电介质中高密度的结构缺陷，热载流子诱导的降解可能伴随着高k薄膜中的电子捕获(C.D. Young等人，IRW，第28页，2003年)(G. Bersuker等人，Materials Today, vol. 26, 2004年1月)。这种在SiO/sub /电介质中没有观察到的大量电子捕获会显著影响晶体管参数，因此，使高k栅极堆叠的热载流子降解特性的评估复杂化。在本文中，我们研究了具有HfSiON栅极介质的poly和TiN栅极nmosfet的热载流子应力的测试条件，以更准确地解决上述问题。
{"title":"Hot carrier reliability of HfSiON NMOSFETs with poly and TiN metal gate","authors":"J. Sim, B. Lee, R. Choi, K. Matthews, D. Kwong, L. Larson, P. Tsui, G. Bersuker","doi":"10.1109/DRC.2004.1367802","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367802","url":null,"abstract":"High-k dielectrics have been proposed to replace SiO/sub 2/ to reduce gate leakage current. Among reliability concerns of the hafnium based metal oxides (Y.H. Kim et al., Tech. Dig. of IEDM, p. 861, 2002) hot carrier effects may represent one of the major limitations for the high-k gate dielectrics introduction (Q. Lu et al., IRPS, p.429, 2002; A. Kumar, VLSI, p. 152, 2003). However, most of the studies did not take into consideration that the hot carriers-induced degradation might be accompanied by the electron trapping in the bulk of the high-k film (C.D. Young et al., IRW, p. 28, 2003) due to the high density of structural defects in the high-k dielectrics (G. Bersuker et al., Materials Today, vol. 26, Jan. 2004). This bulk electron trapping, which is not observed in the case of SiO/sub 2/ dielectrics, can significantly affect transistor parameters and, therefore, complicates evaluation of hot carrier degradation properties of the high-k gate stacks. In this paper, we investigate test conditions for the hot carrier stress of the poly and TiN gate NMOSFETs with HfSiON gate dielectric that would more accurately address the above issues.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124844998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367770
A. Chini, D. Buttari, R. Coffie, L. Shen, T. Palacios, S. Heikman, A. Chakraborty, S. Keller, U. Mishra
GaN-based HEMTs are the most promising device in order to meet the requirements of new generation communication systems. In this work, devices with planar (unrecessed) and gate recessed structures have been fabricated on the same wafer, and characterized by means of RF two-tone measurements at 10 GHz. For GaAs-based devices, increasing device transconductance by means of gate recessing proved to be very effective, resulting in an overall improvement of both large and small signal performance, especially their linearity characteristics. Further optimization of gate recessing may result in higher efficiency operation while maintaining low distortion level.
{"title":"Effect of gate recessing on linearity characteristics of AlGaN/GaN HEMTs","authors":"A. Chini, D. Buttari, R. Coffie, L. Shen, T. Palacios, S. Heikman, A. Chakraborty, S. Keller, U. Mishra","doi":"10.1109/DRC.2004.1367770","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367770","url":null,"abstract":"GaN-based HEMTs are the most promising device in order to meet the requirements of new generation communication systems. In this work, devices with planar (unrecessed) and gate recessed structures have been fabricated on the same wafer, and characterized by means of RF two-tone measurements at 10 GHz. For GaAs-based devices, increasing device transconductance by means of gate recessing proved to be very effective, resulting in an overall improvement of both large and small signal performance, especially their linearity characteristics. Further optimization of gate recessing may result in higher efficiency operation while maintaining low distortion level.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367794
G. Gu, M. Kane, J. Doty, A. Firester
The organic thin film transistor (OTFT) fabrication process has labored under a constraint related to the source/drain contacts, which can be formed either above or below the active layer, referred to, respectively, as top and bottom contact geometries. The top contact geometry is known to provide better performance, e.g., higher field-effect mobilities, but until now only the bottom contact geometry has been compatible with a high level of integration, since the top contact geometry requires patterning of the source/drain metal on top of the organic semiconductor, which can be strongly degraded by typical solvents, rendering it incompatible with photoresist and developers. In this paper, we describe a simple process for simultaneously patterning OTFT top contacts and active layer by photolithography. This is the first report of OTFTs with photolithographically patterned top contacts. The new process closes the gap between the high performance achievable from single devices and that of highly integrated devices.
{"title":"An organic thin-film transistor with photolithographically patterned top contacts and active layer","authors":"G. Gu, M. Kane, J. Doty, A. Firester","doi":"10.1109/DRC.2004.1367794","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367794","url":null,"abstract":"The organic thin film transistor (OTFT) fabrication process has labored under a constraint related to the source/drain contacts, which can be formed either above or below the active layer, referred to, respectively, as top and bottom contact geometries. The top contact geometry is known to provide better performance, e.g., higher field-effect mobilities, but until now only the bottom contact geometry has been compatible with a high level of integration, since the top contact geometry requires patterning of the source/drain metal on top of the organic semiconductor, which can be strongly degraded by typical solvents, rendering it incompatible with photoresist and developers. In this paper, we describe a simple process for simultaneously patterning OTFT top contacts and active layer by photolithography. This is the first report of OTFTs with photolithographically patterned top contacts. The new process closes the gap between the high performance achievable from single devices and that of highly integrated devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115987562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367833
J. Hashizume, F. Koyama
In this paper, we demonstrate the optical near-field enhancement of a metal-aperture GaAs VCSEL with a nanometer-size Au particle. We achieved a record near-field intensity estimated from far-field measurements. Also, we could avoid the polarization dependence of metal-aperture VCSELs by using a symmetric-shaped nano-particle in a metal aperture. Measurement results show that the optical near-field intensity is enhanced by localized surface plasmons excited at the metal particle. We estimated the optical power density to be 5.7 mW//spl mu/M/sup 2/ which is a record high value in near-field VCSELs and is even higher than that of conventional single-mode VCSELs. This enhancement may enable us to use nano-aperture VCSELs with further optimizations for high-density optical storage.
{"title":"Optical near-field enhancement of metal-aperture VCSEL with nano metal particle","authors":"J. Hashizume, F. Koyama","doi":"10.1109/DRC.2004.1367833","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367833","url":null,"abstract":"In this paper, we demonstrate the optical near-field enhancement of a metal-aperture GaAs VCSEL with a nanometer-size Au particle. We achieved a record near-field intensity estimated from far-field measurements. Also, we could avoid the polarization dependence of metal-aperture VCSELs by using a symmetric-shaped nano-particle in a metal aperture. Measurement results show that the optical near-field intensity is enhanced by localized surface plasmons excited at the metal particle. We estimated the optical power density to be 5.7 mW//spl mu/M/sup 2/ which is a record high value in near-field VCSELs and is even higher than that of conventional single-mode VCSELs. This enhancement may enable us to use nano-aperture VCSELs with further optimizations for high-density optical storage.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117069655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367786
Yingda Dong, Z. Griffith, M. Dahlstrom, M. Rodwell
The base-collector junction capacitance (C/sub bc/) is a key factor limiting HBT high frequency performance. To reduce C/sub bc/, we report an HBT structure with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth, the first such structure reported in III-V HBTs. It is designed so that the depleted collector thickness in HBT's extrinsic region is much larger than the depleted collector thickness in HBT's intrinsic region, and therefore substantially reducing the extrinsic base-collector capacitance. Although C/sub bc/ can also be reduced by forming a narrow N+ subcollector stripe lying under the emitter (M. Sokolich et al., 25th IEEE GaAsIC Symp.), such structures can have large collector access resistance Rc arising from long, narrow N+ layer. The collector pedestal structure, however, does not significantly increase collector access resistance relative to a standard mesa structure, and is consequently the approach most widely employed in Si/SiGe technology. We had earlier reported collector pedestal HBTs with low leakage and good DC characteristics (Y. Dong et al., Proc. 2003 Int. Semicond. Dev. Res. Symp., pp. 348-349, 2003); here we report devices with the expected large reduction in C/sub bc/.
基极-集电极结电容(C/sub bc/)是限制HBT高频性能的关键因素。为了降低C/sub bc/，我们采用选择性离子注入和MBE再生的方法，在HBT的本质区下建立了一个集电极基座，这是III-V型HBT中首次报道的这种结构。其设计使得HBT的外源区耗尽集电极厚度远大于HBT的本征区耗尽集电极厚度，从而大大降低了外源基-集电极电容。虽然C/sub bc/也可以通过在发射极下形成一个狭窄的N+子集电极条带来降低(M. Sokolich等人，第25届IEEE GaAsIC会议)，但这种结构可能由于长而窄的N+层而产生较大的集电极接入电阻Rc。然而，与标准台面结构相比，集电极基座结构不会显著增加集电极接入电阻，因此是Si/SiGe技术中最广泛采用的方法。我们早前报道了具有低泄漏和良好直流特性的集电极基座HBTs (Y. Dong et al.， Proc. 2003 Int.)。Semicond。Dev. Res. Symp，第348-349页，2003年);在这里，我们报告了预期C/sub bc/大幅降低的设备。
{"title":"C/sub bc/ reduction in InP heterojunction bipolar transistor with selectively implanted collector pedestal","authors":"Yingda Dong, Z. Griffith, M. Dahlstrom, M. Rodwell","doi":"10.1109/DRC.2004.1367786","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367786","url":null,"abstract":"The base-collector junction capacitance (C/sub bc/) is a key factor limiting HBT high frequency performance. To reduce C/sub bc/, we report an HBT structure with a collector pedestal under the HBT's intrinsic region by using selective ion implantation and MBE regrowth, the first such structure reported in III-V HBTs. It is designed so that the depleted collector thickness in HBT's extrinsic region is much larger than the depleted collector thickness in HBT's intrinsic region, and therefore substantially reducing the extrinsic base-collector capacitance. Although C/sub bc/ can also be reduced by forming a narrow N+ subcollector stripe lying under the emitter (M. Sokolich et al., 25th IEEE GaAsIC Symp.), such structures can have large collector access resistance Rc arising from long, narrow N+ layer. The collector pedestal structure, however, does not significantly increase collector access resistance relative to a standard mesa structure, and is consequently the approach most widely employed in Si/SiGe technology. We had earlier reported collector pedestal HBTs with low leakage and good DC characteristics (Y. Dong et al., Proc. 2003 Int. Semicond. Dev. Res. Symp., pp. 348-349, 2003); here we report devices with the expected large reduction in C/sub bc/.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367852
Y.M. Huang, M. Uppalapati, W. Hancock, T. Jackson
Kinesins are molecular motors that move along microtubules, and provide a model system for force generation that can be exploited for kinesin-powered nano- and micro-machines. Microtubules are /spl sim/25 nm diameter cylindrical polymers of the protein tubulin and can be nm to /spl mu/m long. Kinesins bind to microtubules and use the energy of ATP hydrolysis to walk unidirectionally along them at speeds of /spl sim/1 /spl mu/m/s. In this work, we reverse the typical biological system and move microtubules along surfaces functionalized with kinesin motors. The microtubules then become potential transport vehicles for sensors and lab-on-a-chip applications. A key requirement for extracting useful work from this system is confinement and control of the movement of microtubules over kinesin coated surfaces.
{"title":"Channel confined kinesin-microtubule biomolecular nanomotors","authors":"Y.M. Huang, M. Uppalapati, W. Hancock, T. Jackson","doi":"10.1109/DRC.2004.1367852","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367852","url":null,"abstract":"Kinesins are molecular motors that move along microtubules, and provide a model system for force generation that can be exploited for kinesin-powered nano- and micro-machines. Microtubules are /spl sim/25 nm diameter cylindrical polymers of the protein tubulin and can be nm to /spl mu/m long. Kinesins bind to microtubules and use the energy of ATP hydrolysis to walk unidirectionally along them at speeds of /spl sim/1 /spl mu/m/s. In this work, we reverse the typical biological system and move microtubules along surfaces functionalized with kinesin motors. The microtubules then become potential transport vehicles for sensors and lab-on-a-chip applications. A key requirement for extracting useful work from this system is confinement and control of the movement of microtubules over kinesin coated surfaces.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367880
H. Klauk, M. Halik, U. Zschieschang, F. Eder, G. Schmid, C. Dehm
We have designed and fabricated the first organic complementary integrated circuits on a flexible substrate. Pentacene and hexadecafluorocopperphthalocyanine (F/sub 16/CuPc) were used as the p-type and n-type organic semiconductors, and solution-processed polyvinylphenol was used as the gate dielectric. Transistors and circuits operate with a supply voltage as low as 8 V, and ring oscillators have a signal propagation delay as low as 8 /spl mu/sec per stage. To our knowledge, these are the fastest organic complementary circuits reported to date.
{"title":"An 8V organic complementary logic process for flexible polymeric substrates","authors":"H. Klauk, M. Halik, U. Zschieschang, F. Eder, G. Schmid, C. Dehm","doi":"10.1109/DRC.2004.1367880","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367880","url":null,"abstract":"We have designed and fabricated the first organic complementary integrated circuits on a flexible substrate. Pentacene and hexadecafluorocopperphthalocyanine (F/sub 16/CuPc) were used as the p-type and n-type organic semiconductors, and solution-processed polyvinylphenol was used as the gate dielectric. Transistors and circuits operate with a supply voltage as low as 8 V, and ring oscillators have a signal propagation delay as low as 8 /spl mu/sec per stage. To our knowledge, these are the fastest organic complementary circuits reported to date.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121291835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367900
C. Kuo, M. Payne, J. Anthony, T. Jackson
This work presents fabricated solution processed organic thin film transistors (OTFTs) based on triethylsilylethynyl thienyl pentacene (TES thienyl pentacene) with 1 cm/sup 2//V-s field-effect mobility. The devices also have an on/off current ratio >10/sup 7/ and subthreshold slope near 1 V/decade. To our knowledge, these are the highest mobility solution processed OTFTs demonstrated to date and the first with performance comparable to thermally evaporated pentacene devices.
{"title":"Solution processed OTFTs with 1 cm/sup 2//V-s mobility","authors":"C. Kuo, M. Payne, J. Anthony, T. Jackson","doi":"10.1109/DRC.2004.1367900","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367900","url":null,"abstract":"This work presents fabricated solution processed organic thin film transistors (OTFTs) based on triethylsilylethynyl thienyl pentacene (TES thienyl pentacene) with 1 cm/sup 2//V-s field-effect mobility. The devices also have an on/off current ratio >10/sup 7/ and subthreshold slope near 1 V/decade. To our knowledge, these are the highest mobility solution processed OTFTs demonstrated to date and the first with performance comparable to thermally evaporated pentacene devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116265913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367807
S. Sudirgo, R. Vega, R. P. Nandgaonkar, K. Hirschman, S. Rommel, S. Kurinec, P. Thompson, Niu Jin, P. R. Berger
The incorporation of tunnel diodes with field effect transistors (FET) can improve the speed and power capability in electronic circuitry. This has been realized in III-V materials by demonstrating a low power refresh-free tunneling-SRAM and high performance compact A/D converter. A new thrust to integrate tunnel diodes with the mainstream CMOS technology led to the invention of Si/SiGe resonant interband tunnel diode (RITD) (S.L. Rommel et al., Appl. Phys. Lett., vol. 73, pp. 2191-93, 1998) with the highest reported peak-to-valley current ratio (PVCR) of 6.0 (K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001). The structure consists of a SiGe spacer i-layer sandwiched between two delta-doped planes grown by low-thermal molecular beam epitaxy (LT-MBE) (N. Jin et al., IEEE Trans. Elec. Dev., vol. 50, pp. 1876-1884, 2003). By adjusting the spacer layer thickness, the peak current density (Jp) can be adjusted from 0.1 A/cm/sup 2/ up to 151 kA/cm/sup 2/ (N. Jin et al., App. Phys. Lett., 83, pp. 3308-3310, 2003). Recently, monolithic integration of RITD with CMOS has been realized, demonstrating a low-voltage operation of a monostable-bistable logic element (MOBILE) (S.Sudirgo et al., Proc. 2003 Int. Semic. Dev. Res. Symp., pp. 22, 2003). In this study, RITD layers were grown through openings in a 300 nm thick chemical vapor deposition (CVD) SiO/sub 2/ layer.
隧道二极管与场效应晶体管(FET)的结合可以提高电子电路的速度和功率能力。通过展示低功耗无刷新隧道sram和高性能紧凑型a /D转换器，在III-V材料中实现了这一点。将隧道二极管与主流CMOS技术集成的新推力导致了Si/SiGe谐振带间隧道二极管(RITD)的发明(S.L. Rommel et al.， apple)。理论物理。列托人。(K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001)，最高峰谷电流比(PVCR)为6.0。该结构由夹在两个由低热分子束外延(LT-MBE)生长的δ掺杂平面之间的SiGe间隔层组成(N. Jin等，IEEE Trans.)。《编》，第50卷，第1876—1884页，2003年)。通过调整间隔层厚度，峰值电流密度(Jp)可以从0.1 A/cm/sup 2/调节到151 kA/cm/sup 2/ (N. Jin et al.， App. Phys.)。列托人。， 83, pp. 3308-3310, 2003)。最近，RITD与CMOS的单片集成已经实现，展示了单稳-双稳逻辑元件(MOBILE)的低压操作(S.Sudirgo et al.， Proc. 2003 Int.)。Semic。Dev. Res. Symp，第22页，2003)。在这项研究中，RITD层通过300 nm厚的化学气相沉积(CVD) SiO/sub 2/层的开孔生长。
{"title":"Overgrown Si/SiGe resonant interband tunnel diodes for integration with CMOS","authors":"S. Sudirgo, R. Vega, R. P. Nandgaonkar, K. Hirschman, S. Rommel, S. Kurinec, P. Thompson, Niu Jin, P. R. Berger","doi":"10.1109/DRC.2004.1367807","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367807","url":null,"abstract":"The incorporation of tunnel diodes with field effect transistors (FET) can improve the speed and power capability in electronic circuitry. This has been realized in III-V materials by demonstrating a low power refresh-free tunneling-SRAM and high performance compact A/D converter. A new thrust to integrate tunnel diodes with the mainstream CMOS technology led to the invention of Si/SiGe resonant interband tunnel diode (RITD) (S.L. Rommel et al., Appl. Phys. Lett., vol. 73, pp. 2191-93, 1998) with the highest reported peak-to-valley current ratio (PVCR) of 6.0 (K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001). The structure consists of a SiGe spacer i-layer sandwiched between two delta-doped planes grown by low-thermal molecular beam epitaxy (LT-MBE) (N. Jin et al., IEEE Trans. Elec. Dev., vol. 50, pp. 1876-1884, 2003). By adjusting the spacer layer thickness, the peak current density (Jp) can be adjusted from 0.1 A/cm/sup 2/ up to 151 kA/cm/sup 2/ (N. Jin et al., App. Phys. Lett., 83, pp. 3308-3310, 2003). Recently, monolithic integration of RITD with CMOS has been realized, demonstrating a low-voltage operation of a monostable-bistable logic element (MOBILE) (S.Sudirgo et al., Proc. 2003 Int. Semic. Dev. Res. Symp., pp. 22, 2003). In this study, RITD layers were grown through openings in a 300 nm thick chemical vapor deposition (CVD) SiO/sub 2/ layer.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367795
C. Kuo, T. Jackson
Recent organic thin-film transistor (OTFT) research has focused on real applications for flat panel displays, smart cards, and smart inventory tags, often based on small molecule organic semiconductors such as pentacene. A resolution of 1 /spl mu/m in the fabrication of OTFTs is required for these purposes. It has been a major challenge to fabricate top contacts on the organic semiconductors, based on the fact that devices usually have a lower contact resistance than that of organic devices with bottom contacts. In this paper, we report the fabrication process of lithographic source/drain top contacts of pentacene OTFTs with mobility greater than 0.3 CM/sup 2//V-s. To our best knowledge this is the first work of directly patterning top contacts on OTFTs and demonstrating the desired performance for applications.
{"title":"Directly lithographic top contacts for pentacene organic thin-film transistors","authors":"C. Kuo, T. Jackson","doi":"10.1109/DRC.2004.1367795","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367795","url":null,"abstract":"Recent organic thin-film transistor (OTFT) research has focused on real applications for flat panel displays, smart cards, and smart inventory tags, often based on small molecule organic semiconductors such as pentacene. A resolution of 1 /spl mu/m in the fabrication of OTFTs is required for these purposes. It has been a major challenge to fabricate top contacts on the organic semiconductors, based on the fact that devices usually have a lower contact resistance than that of organic devices with bottom contacts. In this paper, we report the fabrication process of lithographic source/drain top contacts of pentacene OTFTs with mobility greater than 0.3 CM/sup 2//V-s. To our best knowledge this is the first work of directly patterning top contacts on OTFTs and demonstrating the desired performance for applications.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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