Test set compaction procedure for combinational circuits based on decomposition tree

Abstract

In this paper a procedure of compaction a test set for combinational circuits is considered. The compaction procedure is oriented to a test set that represented as set of test cubes. The main idea of compaction a test cubes is to find all maximally compatible subsets by constructing decomposition tree. An irredundant cover of test cubes by all maximally compatible subsets allows finding minimal or close to minimal size of test pattern setting. Experimental results for benchmark circuits demonstrate the efficiency of the suggested compaction procedure.