C. Wardle, C. R. Watson, C. A. Wilson, J. Mudge, B. Nelson
{"title":"A Declarative Design Approach for Combining Macrocells by Directed Placement and Constructive Routing","authors":"C. Wardle, C. R. Watson, C. A. Wilson, J. Mudge, B. Nelson","doi":"10.1109/DAC.1984.1585858","DOIUrl":null,"url":null,"abstract":"This paper describes Sprint, an IC design system. Sprint is an integrated, hierarchical approach to VLSI design. All nodes (cells) in the hierarchy are abstracted in terms of their structural, electrical, and functional properties. Cells may be of arbitrary size and aspect ratio. The relative placement of cells is specified by the designer, and signal and power routing is automatically generated. Sprint has been successfully used by a six-person team to design a 100,000 transistor chip. The chip has been fabricated in a 2.5 micron, double layer metal, HMOS process.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st Design Automation Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1984.1585858","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes Sprint, an IC design system. Sprint is an integrated, hierarchical approach to VLSI design. All nodes (cells) in the hierarchy are abstracted in terms of their structural, electrical, and functional properties. Cells may be of arbitrary size and aspect ratio. The relative placement of cells is specified by the designer, and signal and power routing is automatically generated. Sprint has been successfully used by a six-person team to design a 100,000 transistor chip. The chip has been fabricated in a 2.5 micron, double layer metal, HMOS process.
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