Defect level estimation for digital ICs

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1992-11-04 DOI:10.1109/DFTVS.1992.224363

J. Sousa, João Paulo Teixeira

引用次数: 12

Abstract

Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach.<>

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数字集成电路缺陷水平估计

缺陷水平(DL)预测对于决定测试质量和集成电路(IC)产品的市场竞争力非常重要。然而，目前在IC设计环境中，由于没有使用准确的故障模型，没有办法准确预测DL。本文提出了一种基于接近物理缺陷的实际故障模型的深度深度估计的形式和方法。引入了加权故障覆盖率的定义，并对Williams公式进行了推广，用于处理非等概率故障。将该方法应用于一组实际集成电路设计实例的结果证实了该方法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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