Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224366
C. Thibeault, Y. Savaria
To date, many models have been developed to predict the yield of defect-tolerant integrated circuits (ICs). In this paper, results obtained from several of these models are compared. Their sensitivity to various model parameters is also examined. These results lead one to conclude that, despite differences in the predicted amount of redundancy, it may be possible to obtain good solutions. The differences in the solutions come from the models as well as from the parameters used in these models, and solutions are said to be good when the resulting figures of merit are rather insensitive. Consequently, a simple method is proposed to select the number of spares to add in defect-tolerant ICs.<>
{"title":"Comparing results from defect-tolerant yield models","authors":"C. Thibeault, Y. Savaria","doi":"10.1109/DFTVS.1992.224366","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224366","url":null,"abstract":"To date, many models have been developed to predict the yield of defect-tolerant integrated circuits (ICs). In this paper, results obtained from several of these models are compared. Their sensitivity to various model parameters is also examined. These results lead one to conclude that, despite differences in the predicted amount of redundancy, it may be possible to obtain good solutions. The differences in the solutions come from the models as well as from the parameters used in these models, and solutions are said to be good when the resulting figures of merit are rather insensitive. Consequently, a simple method is proposed to select the number of spares to add in defect-tolerant ICs.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126614935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224371
G. Buonanno, D. Sciuto
A method based on the detectability of bridging faults through test sets developed to locate other types of faults is presented. In particular it will be shown how bridging faults can be detected in CMOS combinational circuits using a test procedure that detects transistor stuck-at faults in a new design for testability for fully CMOS logic. The detection of more than 95% of the possible bridging faults (single and multiple) is achieved.<>
{"title":"Bridging faults modeling and detection in CMOS combinational gates","authors":"G. Buonanno, D. Sciuto","doi":"10.1109/DFTVS.1992.224371","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224371","url":null,"abstract":"A method based on the detectability of bridging faults through test sets developed to locate other types of faults is presented. In particular it will be shown how bridging faults can be detected in CMOS combinational circuits using a test procedure that detects transistor stuck-at faults in a new design for testability for fully CMOS logic. The detection of more than 95% of the possible bridging faults (single and multiple) is achieved.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114393270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224354
D. Walker
Defect tolerance is traditionally concerned with maintaining system function in the face of spot defects that cause catastrophic circuit faults, such as shorts and opens. This paper describes the problem of spot defects that cause delay faults, and how they can be modeled and characterized in an IC fabrication line. A procedure for simulating the occurrence of such delay faults in a design is described, and results for a number of examples are given. Some techniques for tolerance of delay faults at the architectural and algorithmic level are described.<>
{"title":"Tolerance of delay faults","authors":"D. Walker","doi":"10.1109/DFTVS.1992.224354","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224354","url":null,"abstract":"Defect tolerance is traditionally concerned with maintaining system function in the face of spot defects that cause catastrophic circuit faults, such as shorts and opens. This paper describes the problem of spot defects that cause delay faults, and how they can be modeled and characterized in an IC fabrication line. A procedure for simulating the occurrence of such delay faults in a design is described, and results for a number of examples are given. Some techniques for tolerance of delay faults at the architectural and algorithmic level are described.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128756213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224344
D.M. Wu, R. Doney
Describes an implementation of chip built-in self-test using by-pass boundary scan design. This basic structure is then modified to implement a universal self-test structure for cards, boxes and systems.<>
{"title":"A universal self-test design for chip, card and system","authors":"D.M. Wu, R. Doney","doi":"10.1109/DFTVS.1992.224344","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224344","url":null,"abstract":"Describes an implementation of chip built-in self-test using by-pass boundary scan design. This basic structure is then modified to implement a universal self-test structure for cards, boxes and systems.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115878580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224379
C. Low, H. Leong
The problem of reconfiguring memory arrays using spare rows and spare columns has received a great deal of attention in recent years. However, most of the existing research assumes that the array contains only stuck-at faults. This paper, addresses the problem of reconfiguring memory arrays containing both stuck-at faults and coupling faults. The authors present a probabilistic model for studying this problem which is known to be NP-complete. In this model, they distinguish between two classes of faults, namely the class of stuck-at faults and the class of coupling faults. All faulty cells in an array are assumed to independently distributed. The authors first present a bound on the probabilities of occurrence of these two classes of faults that will allow almost all problem instances to be reparable. They also present a bound on these probabilities of defects that will make reconfiguration almost impossible. Empirical study is carried out to validate theoretical results and to investigate the nature of problem instances with probabilities of defects that do not fall within the theoretical bounds.<>
{"title":"Probabilistic analysis of memory reconfiguration in the presence of coupling faults","authors":"C. Low, H. Leong","doi":"10.1109/DFTVS.1992.224379","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224379","url":null,"abstract":"The problem of reconfiguring memory arrays using spare rows and spare columns has received a great deal of attention in recent years. However, most of the existing research assumes that the array contains only stuck-at faults. This paper, addresses the problem of reconfiguring memory arrays containing both stuck-at faults and coupling faults. The authors present a probabilistic model for studying this problem which is known to be NP-complete. In this model, they distinguish between two classes of faults, namely the class of stuck-at faults and the class of coupling faults. All faulty cells in an array are assumed to independently distributed. The authors first present a bound on the probabilities of occurrence of these two classes of faults that will allow almost all problem instances to be reparable. They also present a bound on these probabilities of defects that will make reconfiguration almost impossible. Empirical study is carried out to validate theoretical results and to investigate the nature of problem instances with probabilities of defects that do not fall within the theoretical bounds.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130847941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224376
V. Piuri, M. Sami, R. Stefanelli
A number of digital implementations of neural networks have been presented in recent literature. Moreover, several authors have dealt with the problem of fault tolerance; whether such aim is achieved by techniques typical of the neural computation (e.g. by repeated learning) or by architecture-specific solutions, the first basic step consists clearly in diagnosing the faulty elements. The present paper suggests adoption of concurrent error detection; the granularity chosen to identify faults is that of the neuron. An approach based on a class of arithmetic codes is suggested; various different solutions are discussed, and their relative performances and costs are evaluated. To check the validity of the approach, its application is examined with reference to multi-layered feed-forward networks.<>
{"title":"Arithmetic codes for concurrent error detection in artificial neural networks: the case of AN+B codes","authors":"V. Piuri, M. Sami, R. Stefanelli","doi":"10.1109/DFTVS.1992.224376","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224376","url":null,"abstract":"A number of digital implementations of neural networks have been presented in recent literature. Moreover, several authors have dealt with the problem of fault tolerance; whether such aim is achieved by techniques typical of the neural computation (e.g. by repeated learning) or by architecture-specific solutions, the first basic step consists clearly in diagnosing the faulty elements. The present paper suggests adoption of concurrent error detection; the granularity chosen to identify faults is that of the neuron. An approach based on a class of arithmetic codes is suggested; various different solutions are discussed, and their relative performances and costs are evaluated. To check the validity of the approach, its application is examined with reference to multi-layered feed-forward networks.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224357
D. Blight, R. McLeod
Presents new adaptive routing algorithms for faulty processor arrays. Past research has shown that packet switched based communication performance in mesh connected networks is significantly degraded by the presence of faulty processors. Nondeterministic routing algorithms have been developed based on transport modeling of packet flow in disordered arrays. By utilizing nondeterministic routing strategies, based on biased random walkers, one can implement deadlock free routing, at the expense of not following the shortest path. These algorithms will be shown to be capable of increasing network bandwidth in the presence of faulty processors and interconnects. These algorithms offer an alternative to conventional adaptive routing techniques by utilizing a computationally simple algorithm based on local (nearest neighbor) information. Although the authors concentrate efforts on 2-dimensional processor arrays, the algorithms are also suitable for higher dimensional topologies such as hypercubes.<>
{"title":"Nondeterministic adaptive routing techniques for WSI processor arrays","authors":"D. Blight, R. McLeod","doi":"10.1109/DFTVS.1992.224357","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224357","url":null,"abstract":"Presents new adaptive routing algorithms for faulty processor arrays. Past research has shown that packet switched based communication performance in mesh connected networks is significantly degraded by the presence of faulty processors. Nondeterministic routing algorithms have been developed based on transport modeling of packet flow in disordered arrays. By utilizing nondeterministic routing strategies, based on biased random walkers, one can implement deadlock free routing, at the expense of not following the shortest path. These algorithms will be shown to be capable of increasing network bandwidth in the presence of faulty processors and interconnects. These algorithms offer an alternative to conventional adaptive routing techniques by utilizing a computationally simple algorithm based on local (nearest neighbor) information. Although the authors concentrate efforts on 2-dimensional processor arrays, the algorithms are also suitable for higher dimensional topologies such as hypercubes.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224356
C. Stapper
Stochastic fault simulation processes have been used successfully to generate fault distributions for evaluating fault tolerant VLSI designs. In one of these processes, faults in subareas of integrated circuits are simulated as a function of time. This leads to an exponential increase of the average number of faults in the area segments of the integrated circuits. It was discovered analytically that by forcing a correlation between the number of faults in adjacent area segments, the increase in the number of faults with time exceeds exponential growth and exhibits a singularity. At the singularity point the fault population becomes infinite. The time associated with this singularity has been denoted as 'saturation time'.<>
{"title":"Spatial fault simulation and the saturation effect","authors":"C. Stapper","doi":"10.1109/DFTVS.1992.224356","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224356","url":null,"abstract":"Stochastic fault simulation processes have been used successfully to generate fault distributions for evaluating fault tolerant VLSI designs. In one of these processes, faults in subareas of integrated circuits are simulated as a function of time. This leads to an exponential increase of the average number of faults in the area segments of the integrated circuits. It was discovered analytically that by forcing a correlation between the number of faults in adjacent area segments, the increase in the number of faults with time exceeds exponential growth and exhibits a singularity. At the singularity point the fault population becomes infinite. The time associated with this singularity has been denoted as 'saturation time'.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224372
A. DeHon
The acceptance and use of standard scan-based test access ports (TAPs), such as the IEEE-1149.1-1990 standard, have begun to ease the task of system testability and in-circuit diagnostics. The typical singular nature of these TAPs along with the all-or-nothing manner in which test facilities are accessed make such standard TAPs inappropriate for use in fault-tolerant architectures. The authors propose three simple additions to standard scan practices which allow scan techniques to be effectively utilized in fault-tolerant environments. Specifically, they advocate the incorporation of multiple-TAPs, port-by-port selection control, and partial external scan. Multi-TAP construction offers tolerance to faults in the scan path or circuitry. Port-by-port selection and partial external scan allow fault-diagnostics which are minimally intrusive and in-operation reconfiguration for fault-masking and repair.<>
{"title":"Scan-based testability for fault-tolerant architectures","authors":"A. DeHon","doi":"10.1109/DFTVS.1992.224372","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224372","url":null,"abstract":"The acceptance and use of standard scan-based test access ports (TAPs), such as the IEEE-1149.1-1990 standard, have begun to ease the task of system testability and in-circuit diagnostics. The typical singular nature of these TAPs along with the all-or-nothing manner in which test facilities are accessed make such standard TAPs inappropriate for use in fault-tolerant architectures. The authors propose three simple additions to standard scan practices which allow scan techniques to be effectively utilized in fault-tolerant environments. Specifically, they advocate the incorporation of multiple-TAPs, port-by-port selection control, and partial external scan. Multi-TAP construction offers tolerance to faults in the scan path or circuitry. Port-by-port selection and partial external scan allow fault-diagnostics which are minimally intrusive and in-operation reconfiguration for fault-masking and repair.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129578504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224355
J. P. de Gyvez, S. Dani
Although the majority of defects found in manufacturing lines have predominantly 2-Dimensional effects, there are many situations in which 2D defect models do not suffice, e.g. tall layer bulks disrupting the continuity of subsequent layers, abrupt surface topologies, extraneous materials embedded in the IC, etc. In this paper, a procedure to capture the catastrophic effect of 3-Dimensional defects is presented. This approach is based on the geometrical properties that result from the interaction between IC and defect size in two coordinate spaces: x-y and z. The approach is a natural extension to the concept of critical areas, namely, the extraction of critical volumes. Through the course of this work hints to the origins of 3D defects will be given, conditions to capture critical volumes will be developed, and it will be shown that the net effect of 3D defects is accumulated from layer to layer.<>
{"title":"Modeling of 3-dimensional defects in integrated circuits","authors":"J. P. de Gyvez, S. Dani","doi":"10.1109/DFTVS.1992.224355","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224355","url":null,"abstract":"Although the majority of defects found in manufacturing lines have predominantly 2-Dimensional effects, there are many situations in which 2D defect models do not suffice, e.g. tall layer bulks disrupting the continuity of subsequent layers, abrupt surface topologies, extraneous materials embedded in the IC, etc. In this paper, a procedure to capture the catastrophic effect of 3-Dimensional defects is presented. This approach is based on the geometrical properties that result from the interaction between IC and defect size in two coordinate spaces: x-y and z. The approach is a natural extension to the concept of critical areas, namely, the extraction of critical volumes. Through the course of this work hints to the origins of 3D defects will be given, conditions to capture critical volumes will be developed, and it will be shown that the net effect of 3D defects is accumulated from layer to layer.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126705874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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