Realistic fault models and test procedure for multi-port SRAMs

Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2001-08-06 DOI:10.1109/MTDT.2001.945230

S. Hamdioui, A. V. Goor, D. Eastwick, M. Rodgers

引用次数: 6

Abstract

This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ... , p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of.

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多端口sram的实际故障模型和测试程序

基于缺陷注入和SPICE仿真，提出了具有p端口的多端口存储器的真实故障模型。结果表明，p口存储器的故障模型可分为单口故障、双口故障、双口故障等p类。， p端口故障。此外，本文还讨论了这种存储器的测试程序。结果表明，所需检验的时间复杂度不是与p成指数比例，而是线性的，正如不同作者所发表的那样;无论多端口内存由多少个端口组成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing

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