Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945221
G. Harling
System-on-Chip (SoC) designs will soon be dominated by on-chip memory so there is an urgent need for customization of memory semiconductor intellectual property (SIP) to increase product differentiation. This paper describes a software compiler tool which can be used to customize DRAM memory arrays in both pure logic and merged logic processes. This compiler optimizes memory macrocells for speed, power, and area to obtain radically reduced area and power when compared to SRAM implementations. It can also create custom memories with very fine granularity.
{"title":"A DRAM compiler for fully optimized memory instances","authors":"G. Harling","doi":"10.1109/MTDT.2001.945221","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945221","url":null,"abstract":"System-on-Chip (SoC) designs will soon be dominated by on-chip memory so there is an urgent need for customization of memory semiconductor intellectual property (SIP) to increase product differentiation. This paper describes a software compiler tool which can be used to customize DRAM memory arrays in both pure logic and merged logic processes. This compiler optimizes memory macrocells for speed, power, and area to obtain radically reduced area and power when compared to SRAM implementations. It can also create custom memories with very fine granularity.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945227
S. Gregori, G. Torelli, O. Khouri, R. Micheloni
Presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different "bit-layers", which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead on memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.
{"title":"An error control code scheme for multilevel Flash memories","authors":"S. Gregori, G. Torelli, O. Khouri, R. Micheloni","doi":"10.1109/MTDT.2001.945227","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945227","url":null,"abstract":"Presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different \"bit-layers\", which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead on memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129671331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945233
F. Karimi, F. Lombardi, V. S. Irrinki, T. Crosby
This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.
{"title":"A parallel approach for testing multi-port static random access memories","authors":"F. Karimi, F. Lombardi, V. S. Irrinki, T. Crosby","doi":"10.1109/MTDT.2001.945233","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945233","url":null,"abstract":"This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945226
S. Matarrese, L. Fasoli
Presents a method to calculate the redundancy coverage for FLASH memory. The method can be used to compare different redundancy architectures and gives the probability of repairing a certain number of random failures. After a brief introduction, the hypothesis and the method are presented. Some illustrative examples are provided.
{"title":"A method to calculate redundancy coverage for FLASH memories","authors":"S. Matarrese, L. Fasoli","doi":"10.1109/MTDT.2001.945226","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945226","url":null,"abstract":"Presents a method to calculate the redundancy coverage for FLASH memory. The method can be used to compare different redundancy architectures and gives the probability of repairing a certain number of random failures. After a brief introduction, the hypothesis and the method are presented. Some illustrative examples are provided.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945223
R. Sung, J. C. Koob, T. Brandon, D. Elliott, B. Cockburn
We describe the design of an embedded 128-Kb Silicon-On-Insulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25-/spl mu/m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presented. The impact of the floating body effect is investigated for both memory reads and writes. We describe threshold mismatch effects in the sense amplifier that result from the floating body voltage. Floating body effects are compared against simulated results for an SRAM designed in a 0.25-/spl mu/m partially-depleted SOI process.
{"title":"Design of an embedded fully-depleted SOI SRAM","authors":"R. Sung, J. C. Koob, T. Brandon, D. Elliott, B. Cockburn","doi":"10.1109/MTDT.2001.945223","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945223","url":null,"abstract":"We describe the design of an embedded 128-Kb Silicon-On-Insulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25-/spl mu/m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presented. The impact of the floating body effect is investigated for both memory reads and writes. We describe threshold mismatch effects in the sense amplifier that result from the floating body voltage. Floating body effects are compared against simulated results for an SRAM designed in a 0.25-/spl mu/m partially-depleted SOI process.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945228
S. Shoukourian, V. Vardanian, Y. Zorian
An approach for design and evaluation of redundancy analysis algorithms based on vectors of preferences is proposed for memory devices with spare elements. Experiments on the application of the new algorithms for self-test and repair (STAR) type SRAM memories have shown the efficiency of the proposed approach.
{"title":"An approach for evaluation of redundancy analysis algorithms","authors":"S. Shoukourian, V. Vardanian, Y. Zorian","doi":"10.1109/MTDT.2001.945228","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945228","url":null,"abstract":"An approach for design and evaluation of redundancy analysis algorithms based on vectors of preferences is proposed for memory devices with spare elements. Experiments on the application of the new algorithms for self-test and repair (STAR) type SRAM memories have shown the efficiency of the proposed approach.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126704029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945236
O. Khouri, S. Gregori, Dario Soltesz, G. Torelli, R. Micheloni
This paper presents a charge pump voltage multiplier for flash memory programming. Its key feature is a low output resistance. As compared to conventional solutions, the charge pump proposed can either deliver an increased output current to drive the memory bit-lines during programming, or deliver the same amount of current with a decreased area occupation. The output resistance reduction is achieved by using boosting techniques in the phase driver. This approach reduces the time constant of the charge transfer between the pump stages, thereby allowing the use of an adequately high clock frequency to control the pump operation. Simulation results showed the validity of the proposed approach.
{"title":"Low output resistance charge pump for flash memory programming","authors":"O. Khouri, S. Gregori, Dario Soltesz, G. Torelli, R. Micheloni","doi":"10.1109/MTDT.2001.945236","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945236","url":null,"abstract":"This paper presents a charge pump voltage multiplier for flash memory programming. Its key feature is a low output resistance. As compared to conventional solutions, the charge pump proposed can either deliver an increased output current to drive the memory bit-lines during programming, or deliver the same amount of current with a decreased area occupation. The output resistance reduction is achieved by using boosting techniques in the phase driver. This approach reduces the time constant of the charge transfer between the pump stages, thereby allowing the use of an adequately high clock frequency to control the pump operation. Simulation results showed the validity of the proposed approach.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121547774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945229
Z. Al-Ars, A. V. Goor
Memory fault models have always been considered not to change with time. Therefore, tests constructed to detect sensitized faults need not take into consideration the time period between sensitizing and detecting the fault. In this paper; a new class of memory fault models is presented, where the time between sensitizing and detection should be considered. The paper also presents fault analysis results, based on defect injection and simulation, where transient faults have been observed. The impact of transient faults on testing is discussed and new detection conditions, in combination with a test, are given.
{"title":"Transient faults in DRAMs: concept, analysis and impact on tests","authors":"Z. Al-Ars, A. V. Goor","doi":"10.1109/MTDT.2001.945229","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945229","url":null,"abstract":"Memory fault models have always been considered not to change with time. Therefore, tests constructed to detect sensitized faults need not take into consideration the time period between sensitizing and detecting the fault. In this paper; a new class of memory fault models is presented, where the time between sensitizing and detection should be considered. The paper also presents fault analysis results, based on defect injection and simulation, where transient faults have been observed. The impact of transient faults on testing is discussed and new detection conditions, in combination with a test, are given.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129315528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945235
Xiaoling Sun, Jian Xu, P. Trouborst
The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by the integrity of all its components. It has been found that the minimum numbers of CLM test configurations (TCs) under single stuck-at, multiple stuck-at, and universal fault models are six, seven and eight respectively. A set of selection criteria was proposed to obtain the "best" of eight TCs, each contains a subset of six and seven TCs for the two stuck-at fault models. These CLM TCs can be extended to include the test of the whole CLB.
{"title":"Testing carry logic modules of SRAM-based FPGAs","authors":"Xiaoling Sun, Jian Xu, P. Trouborst","doi":"10.1109/MTDT.2001.945235","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945235","url":null,"abstract":"The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by the integrity of all its components. It has been found that the minimum numbers of CLM test configurations (TCs) under single stuck-at, multiple stuck-at, and universal fault models are six, seven and eight respectively. A set of selection criteria was proposed to obtain the \"best\" of eight TCs, each contains a subset of six and seven TCs for the two stuck-at fault models. These CLM TCs can be extended to include the test of the whole CLB.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125181123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-08-06DOI: 10.1109/MTDT.2001.945230
S. Hamdioui, A. V. Goor, D. Eastwick, M. Rodgers
This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ... , p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of.
{"title":"Realistic fault models and test procedure for multi-port SRAMs","authors":"S. Hamdioui, A. V. Goor, D. Eastwick, M. Rodgers","doi":"10.1109/MTDT.2001.945230","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945230","url":null,"abstract":"This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ... , p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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