A 13. 8 μW Wake-Up Receiver With 0.4 mVpp Sensitivity For Low Frequency Applications

Abstract

In this paper, a low power low frequency (LF) wake-up receiver was presented. To achieve high sensitivity, a selective amplifier, implemented in an architecture of three-stage fully differential cascade amplifier, utilized neutralization technique and high pass filters to achieve a maximum gain of 50 dB at 125 kHz while maintaining low power. The whole receiver was designed and fabricated in SMIC 0.18 $\mu$m CMOS process with a total size of 0.96 m$\mathrm{m}^{2}$. As a result, the measurements showed that the design achieved a sensitivity of 0.4 mVpp while dissipating just 4.2 $\mu$A from a 3.3 V supply voltage.