{"title":"A novel approach for constrained via minimization problem in VLSI channel routing","authors":"B. Das, Ashim kumar Mahato, Ajoy Kumar Khan","doi":"10.1109/EDCAV.2015.7060556","DOIUrl":null,"url":null,"abstract":"Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDCAV.2015.7060556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.
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