Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060544
S. K. Panda, P. K. Jana
Cloud Computing has become a popular computing paradigm which has gained enormous attention in delivering on-demand services. Task scheduling in cloud computing is an important issue that has been well researched and many algorithms have been developed for the same. However, the goal of most of these algorithms is to minimize the overall completion time (i.e., makespan) without looking into minimization of the overall cost of the service (referred as budget). Moreover, many of them are applicable to single-cloud environment. In this paper, we propose a multi-objective task scheduling algorithm for heterogeneous multi-cloud environment which takes care both these issues. We perform rigorous experiments on some synthetic and benchmark data sets. The experimental results show that the proposed algorithm balances both the makespan and total cost in contrast to two existing task scheduling algorithms in terms of various performance metrics including makespan, total cost and average cloud utilization.
{"title":"A multi-objective task scheduling algorithm for heterogeneous multi-cloud environment","authors":"S. K. Panda, P. K. Jana","doi":"10.1109/EDCAV.2015.7060544","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060544","url":null,"abstract":"Cloud Computing has become a popular computing paradigm which has gained enormous attention in delivering on-demand services. Task scheduling in cloud computing is an important issue that has been well researched and many algorithms have been developed for the same. However, the goal of most of these algorithms is to minimize the overall completion time (i.e., makespan) without looking into minimization of the overall cost of the service (referred as budget). Moreover, many of them are applicable to single-cloud environment. In this paper, we propose a multi-objective task scheduling algorithm for heterogeneous multi-cloud environment which takes care both these issues. We perform rigorous experiments on some synthetic and benchmark data sets. The experimental results show that the proposed algorithm balances both the makespan and total cost in contrast to two existing task scheduling algorithms in terms of various performance metrics including makespan, total cost and average cloud utilization.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125446932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060557
Shreyasee Debnath, Manashwi Tamuli, Ashok Ray, G. Trivedi
Conjugate Gradient method is a very efficient iterative method for solving large systems of equations arising from real life scientific computing applications. In this paper we present the Conjugate Gradient method and its variants in brief. We also present a comparative analysis of implementations of this method on various platforms like FPGAs, GPUs etc which are suitable for High Performance Computing.
{"title":"A review on accelerating scientific computations using the Conjugate Gradient method","authors":"Shreyasee Debnath, Manashwi Tamuli, Ashok Ray, G. Trivedi","doi":"10.1109/EDCAV.2015.7060557","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060557","url":null,"abstract":"Conjugate Gradient method is a very efficient iterative method for solving large systems of equations arising from real life scientific computing applications. In this paper we present the Conjugate Gradient method and its variants in brief. We also present a comparative analysis of implementations of this method on various platforms like FPGAs, GPUs etc which are suitable for High Performance Computing.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060546
Biswajit Langthasa, Bikash Acharya, S. Sarmah
Classification of Network Traffic is one of most important issue in network management and detection of Intrusion attacks play a vital role in it. To have a holistic picture of the network intrusion detection, selection of appropriate feature is very important; it reduces analysis effort and time too. Data mining can be very fruitful for feature selection and intrusion detection. In this paper, Tcpdump is used to capture network traffic and visualize different set of features using k-mean clustering. KDD'99 corrected intrusion detection dataset is evaluated to find out most important and relevant features and an algorithm based on the features is proposed to detect different types of dos, probing, u2r and r2l attacks with an accuracy of more than 80%.
{"title":"Classification of network traffic in LAN","authors":"Biswajit Langthasa, Bikash Acharya, S. Sarmah","doi":"10.1109/EDCAV.2015.7060546","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060546","url":null,"abstract":"Classification of Network Traffic is one of most important issue in network management and detection of Intrusion attacks play a vital role in it. To have a holistic picture of the network intrusion detection, selection of appropriate feature is very important; it reduces analysis effort and time too. Data mining can be very fruitful for feature selection and intrusion detection. In this paper, Tcpdump is used to capture network traffic and visualize different set of features using k-mean clustering. KDD'99 corrected intrusion detection dataset is evaluated to find out most important and relevant features and an algorithm based on the features is proposed to detect different types of dos, probing, u2r and r2l attacks with an accuracy of more than 80%.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126253206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060535
Pramod Srinivasan, Anirudha Bhat, Sneh Lata Murotiya, Anu Gupta
Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising alternative to conventional CMOS design owing to the better electrostatic control and high mobility. The paper presents a novel design of 10 Transistor ternary memory cell, with separate read and write lines. Extensive HSPICE simulations have validated the read-write functionality of the design. Besides a significant reduction in transistor count, results show at least 45% reduction in delay as compared to prevalent memory cell designs.
{"title":"Design and performance evaluation of a low transistor ternary CNTFET SRAM cell","authors":"Pramod Srinivasan, Anirudha Bhat, Sneh Lata Murotiya, Anu Gupta","doi":"10.1109/EDCAV.2015.7060535","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060535","url":null,"abstract":"Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising alternative to conventional CMOS design owing to the better electrostatic control and high mobility. The paper presents a novel design of 10 Transistor ternary memory cell, with separate read and write lines. Extensive HSPICE simulations have validated the read-write functionality of the design. Besides a significant reduction in transistor count, results show at least 45% reduction in delay as compared to prevalent memory cell designs.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121399791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060545
Md. Abdul Barik, M. Sarma, J. C. Dutta
The present study compares the traditional field effect transistors with newly developed junctionless carbon nanotube field effect transistor (JLCNTFET) for cholesterol detection. JLCNTFET has been fabricated using electrochemical deposition (ECD) technique on indium tin oxide (ITO) coated glass. A digital multimeter (DMM) has been used for measurement of cholesterol response in a glass pot containing phosphate buffer saline (PBS). The response study implies that JLCNTFET shows improved sensitivity than other for cholesterol detection. From this work, it has been observed that fabrication of junctionless CNTFET is simpler and requires minimal instrument. Therefore, effort has been made to utilize this nano-structured JLCNTFET for estimation of various clinical disorders.
{"title":"Traditional and junctionless field effect transistor for cholesterol detection","authors":"Md. Abdul Barik, M. Sarma, J. C. Dutta","doi":"10.1109/EDCAV.2015.7060545","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060545","url":null,"abstract":"The present study compares the traditional field effect transistors with newly developed junctionless carbon nanotube field effect transistor (JLCNTFET) for cholesterol detection. JLCNTFET has been fabricated using electrochemical deposition (ECD) technique on indium tin oxide (ITO) coated glass. A digital multimeter (DMM) has been used for measurement of cholesterol response in a glass pot containing phosphate buffer saline (PBS). The response study implies that JLCNTFET shows improved sensitivity than other for cholesterol detection. From this work, it has been observed that fabrication of junctionless CNTFET is simpler and requires minimal instrument. Therefore, effort has been made to utilize this nano-structured JLCNTFET for estimation of various clinical disorders.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131516287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060531
A. Majumder, Barnali Chowdhury, Abir J. Mondai, Kunj Jain
Boolean algebra is a set of rules, laws, and theorems by which logical operations can be expressed mathematically. In its application one has to reduce a particular expression to its simplest form. Karnaugh map and Quine McCluskey (Q-M) method are the systematic approach for simplifying and manipulating Boolean expressions. In this paper a simpler approach to minimize logical functions is introduced which will be followed by prime implicant chart as in the Q-M method to reduce the possibility of occurring an error. With this approach the number of gates required to realize a function gets reduced to a great extent with minimum effort as the manipulation is totally based on decimal values. This technique can be used to any number of variables to improve the performance of presently existing methods.
{"title":"Investigation on Quine McCluskey method: A decimal manipulation based novel approach for the minimization of Boolean function","authors":"A. Majumder, Barnali Chowdhury, Abir J. Mondai, Kunj Jain","doi":"10.1109/EDCAV.2015.7060531","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060531","url":null,"abstract":"Boolean algebra is a set of rules, laws, and theorems by which logical operations can be expressed mathematically. In its application one has to reduce a particular expression to its simplest form. Karnaugh map and Quine McCluskey (Q-M) method are the systematic approach for simplifying and manipulating Boolean expressions. In this paper a simpler approach to minimize logical functions is introduced which will be followed by prime implicant chart as in the Q-M method to reduce the possibility of occurring an error. With this approach the number of gates required to realize a function gets reduced to a great extent with minimum effort as the manipulation is totally based on decimal values. This technique can be used to any number of variables to improve the performance of presently existing methods.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125759319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060561
D. Das
The paper describes the work on human gait recognition using Hidden Markov Model (HMM), Support Vector Machine (SVM) and Hybridized classifiers (developed using both HMM and SVM). Human gait data obtained from CASIA gait database were segmented to locate major human body part and generate corresponding stick view in order to extract gait features. A total of 25 features were obtained using the length of body parts and major joint angles along with other features and classified using HMM, SVM and Hybridized classifiers. The Hybridized classifier outperforms individual classifiers by 11.25% and 18.14% during training and testing respectively.
{"title":"Human gait classification using combined HMM & SVM hybrid classifier","authors":"D. Das","doi":"10.1109/EDCAV.2015.7060561","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060561","url":null,"abstract":"The paper describes the work on human gait recognition using Hidden Markov Model (HMM), Support Vector Machine (SVM) and Hybridized classifiers (developed using both HMM and SVM). Human gait data obtained from CASIA gait database were segmented to locate major human body part and generate corresponding stick view in order to extract gait features. A total of 25 features were obtained using the length of body parts and major joint angles along with other features and classified using HMM, SVM and Hybridized classifiers. The Hybridized classifier outperforms individual classifiers by 11.25% and 18.14% during training and testing respectively.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"307 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060529
D. Sarkar, A. Chowdhury
This paper demonstrates a simple, efficient and low cost ECG and heart beat measurement system using PIC18F4550 microcontroller. The design includes LT1028 OP AMP IC based signal conditioning unit. Detected ECG signal inside microcontroller is send to a Lab VIEW based GUI platform with USB CDC protocol and also tested with RS-232 protocol. Signal plotting and heart beat calculation is done inside LabVIEW program. ECG signal can also be viewed from PWM port of PIC18F4550 microcontroller via a low pass filtering stage. The whole design is simulated successfully with Proteus circuit simulator. The ECG signal is extracted in audio format (.WAV) from LabVIEW biomedicai toolkit for ECG simulator keeping 1.2 mV upper voltage limit and -0.4 mV lower voltage limit. The audio file is given as the input to the circuit in Proteus. USB simulation is done with the help of Proteus Virtual USB and Microchip USB CDC driver. RS-232 virtual serial port is created using Eltima virtual serial port software. MPLAB IDE is used as microcontroller program compiler.
{"title":"Low cost and efficient ECG measurement system using PIC18F4550 microcontroller","authors":"D. Sarkar, A. Chowdhury","doi":"10.1109/EDCAV.2015.7060529","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060529","url":null,"abstract":"This paper demonstrates a simple, efficient and low cost ECG and heart beat measurement system using PIC18F4550 microcontroller. The design includes LT1028 OP AMP IC based signal conditioning unit. Detected ECG signal inside microcontroller is send to a Lab VIEW based GUI platform with USB CDC protocol and also tested with RS-232 protocol. Signal plotting and heart beat calculation is done inside LabVIEW program. ECG signal can also be viewed from PWM port of PIC18F4550 microcontroller via a low pass filtering stage. The whole design is simulated successfully with Proteus circuit simulator. The ECG signal is extracted in audio format (.WAV) from LabVIEW biomedicai toolkit for ECG simulator keeping 1.2 mV upper voltage limit and -0.4 mV lower voltage limit. The audio file is given as the input to the circuit in Proteus. USB simulation is done with the help of Proteus Virtual USB and Microchip USB CDC driver. RS-232 virtual serial port is created using Eltima virtual serial port software. MPLAB IDE is used as microcontroller program compiler.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126980275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060541
Apangshu Das, S. Pradhan
Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area So, there is a trade-offs between area and power-density. Previous works has been done on the polarity selection of outputs of programmable logic arrays (PLA) for its reduced area or low power realization. In this paper, we present a heuristic based on genetic algorithm to increase the sharing of product terms in multi-output PLA by selecting the proper output polarity and a suitable area and power-density trade-off has been enumerated. This is the first ever effort to incorporate the power-density in polarity selection process. The proposed algorithm has been validated with the LGSynth93 benchmark circuit. A comparative study of our approach is done with `espresso' and `espresso-Dopo' methodology. We obtained 17.53% (26.69%) improvement in area (power-density) with respect to `espresso'. Also 7.87% in area and 27.95% in power-density with respect to `espresso-Dopo' has been reported in this paper.
{"title":"Thermal aware output polarity selection of programmable logic arrays","authors":"Apangshu Das, S. Pradhan","doi":"10.1109/EDCAV.2015.7060541","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060541","url":null,"abstract":"Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area So, there is a trade-offs between area and power-density. Previous works has been done on the polarity selection of outputs of programmable logic arrays (PLA) for its reduced area or low power realization. In this paper, we present a heuristic based on genetic algorithm to increase the sharing of product terms in multi-output PLA by selecting the proper output polarity and a suitable area and power-density trade-off has been enumerated. This is the first ever effort to incorporate the power-density in polarity selection process. The proposed algorithm has been validated with the LGSynth93 benchmark circuit. A comparative study of our approach is done with `espresso' and `espresso-Dopo' methodology. We obtained 17.53% (26.69%) improvement in area (power-density) with respect to `espresso'. Also 7.87% in area and 27.95% in power-density with respect to `espresso-Dopo' has been reported in this paper.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133633137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060534
H. Singh, T. Bezboruah
We present the design and testing of a 16-bit frequency to digital converter, based on AT89C51 micro-controller, for use in sensing applications. The system generates digital equivalents of frequencies by counting negative transitions of transistor transistor logic signal applied to a designated input of the microcontroller's on-chip counter. The system digitizes frequencies of signal generated from a frequency generator, while the digitized data are logged in a personnel computer via printer port by using a LabVIEW program. The system is found to have a linear response over a large dynamic range of conversion, and its resolution is tunable down to 1.6 Hz. The proposed system can be used as interface circuit for frequency output sensors without relying on frequency to voltage converter and analog to digital converter.
{"title":"Micro-controller based frequency to digital converter for interfacing frequency output sensors","authors":"H. Singh, T. Bezboruah","doi":"10.1109/EDCAV.2015.7060534","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060534","url":null,"abstract":"We present the design and testing of a 16-bit frequency to digital converter, based on AT89C51 micro-controller, for use in sensing applications. The system generates digital equivalents of frequencies by counting negative transitions of transistor transistor logic signal applied to a designated input of the microcontroller's on-chip counter. The system digitizes frequencies of signal generated from a frequency generator, while the digitized data are logged in a personnel computer via printer port by using a LabVIEW program. The system is found to have a linear response over a large dynamic range of conversion, and its resolution is tunable down to 1.6 Hz. The proposed system can be used as interface circuit for frequency output sensors without relying on frequency to voltage converter and analog to digital converter.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131347789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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