Fault injection scan design for enhanced VLSI design verification

Abstract

Proposes a design technique called the fault injection scan register (FISR) for fault injection that has much higher fault coverage than the traditional pin-level fault injection for systems using complex VLSI components. The FISR utilizes the scan-in-scan-out design inject faults to the internal circuits of a VLSI chip. The fault injection is accomplished by loading a pair of fault vectors to a set of fault latches via the scan registers. The fault latches are then enabled so that the target signals will be forced to high or low during the normal operation. the delivery of injected faults via the scan registers and the concept of fault vector are the major innovations in the design. An innovative three stage flip-flop is also used to reduce the implementation overhead of the FISR.<>