{"title":"Timed trace theoretic verification using partial order reduction","authors":"T. Yoneda, Hiroshi Ryu","doi":"10.1109/ASYNC.1999.761527","DOIUrl":null,"url":null,"abstract":"In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1999.761527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28
Abstract
In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.
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