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Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems最新文献

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Bounding average time separations of events in stochastic timed Petri nets with choice 带选择的随机定时Petri网中事件的边界平均时间分离
A. Xie, Sangyun Kim, P. Beerel
This paper presents a technique to estimate the average time separation of events (TSE) in stochastic timed Petri nets that can model time-independent choice and have arbitrary delay distributions associated with places. The approach analyzes finite net unfoldings to derive closed-form expressions for lower and upper bounds on the average TSE, which can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds thus provides an estimate of the average TSE which has a well-defined error bound. Moreover, we can often make the error arbitrarily small by analyzing larger net unfoldings at the cost of additional run-time. Experiments on several asynchronous systems demonstrate the quality of our estimate and the efficiency of the technique. The experiments include the performance analysis of a full-scale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID containing over 900 transitions and 500 places.
本文提出了一种估计随机时间Petri网中事件平均时间间隔(TSE)的方法,该方法可以模拟与时间无关的选择,并且具有与地点相关的任意延迟分布。该方法通过分析有限的网络展开,推导出平均TSE的下界和上界的封闭表达式,可以用标准统计方法有效地评估。由此得出的上界和下界的平均值提供了具有明确定义的误差界的平均TSE的估计。此外,我们通常可以通过分析更大的网络展开,以额外的运行时间为代价,使误差任意小。在几个异步系统上的实验证明了我们估计的质量和技术的有效性。实验包括对包含900多个转换和500多个位置的英特尔异步指令长度解码和转向单元RAPPID的全尺寸Petri网模型的性能分析。
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引用次数: 53
Theoretical limits on the data dependent performance of asynchronous circuits 异步电路数据依赖性能的理论限制
D. Kearney
Speculations about the ability of asynchronous systems to take advantage of the data dependent performance of circuit components have been widespread. Simulations and actual designs have not however provided much confirmation that it is possible to transfer the average case data dependent performance of a single stage into average case performance of a system without paying an unacceptable area penalty in the implementation. Here it is shown that if area*time is chosen as the performance metric to be minimized there are in fact absolute theoretical limits to achieving data dependent performance as compared with synchronous circuits. These limits are shown to arise in two completely different theoretical approaches each of which make few assumptions about the distribution of data dependent delays experienced when the circuit operates. The theoretical approach confirms many of the tradeoffs that designers of data dependent circuits have long suspected.
关于异步系统利用电路元件的数据依赖性能的能力的推测已经广泛存在。然而,模拟和实际设计并没有提供太多的证实,可以将单个阶段的平均情况数据依赖性能转换为系统的平均情况性能,而不会在实现中支付不可接受的区域惩罚。这里显示,如果选择面积*时间作为要最小化的性能指标,实际上与同步电路相比,实现数据依赖性能的绝对理论限制。这些限制显示在两种完全不同的理论方法中出现,每种方法对电路运行时经历的数据相关延迟的分布几乎没有假设。理论方法证实了数据依赖电路设计者长期以来所怀疑的许多权衡。
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引用次数: 14
Projection: a synthesis technique for concurrent systems 投影:并发系统的一种综合技术
R. Manohar, Tak-Kwan Lee, Alain J. Martin
We present a process decomposition technique for the design of pipelined asynchronous circuits. The technique is simple to use, and is based on projecting a program on different sets of variables. We provide conditions under which the technique can be applied, and show how it can be used to decompose complex concurrent programs.
提出了一种用于流水线异步电路设计的过程分解技术。该技术使用简单,基于将程序投影到不同的变量集上。我们提供了可以应用该技术的条件,并展示了如何使用它来分解复杂的并发程序。
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引用次数: 32
Timed trace theoretic verification using partial order reduction 利用偏序约简的时间跟踪理论验证
T. Yoneda, Hiroshi Ryu
In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.
本文对迹理论验证方法进行了偏序约简的扩展,使之能较好地处理定时电路和定时规格。偏序约简算法是由顽固集方法的时间版本得到的。STARI电路的实验结果表明,该方法是有效的。
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引用次数: 28
A design framework for asynchronous/synchronous circuits based on CHP to HDL translation 基于CHP到HDL转换的异步/同步电路设计框架
M. Renaudin, P. Vivet, F. Robin
An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented. It is based on the development of a tool called "CHP/sub 2/VHDL" which automatically translates CSP-like specifications (Communicating Sequential Processes) into VHDL programs. This work follows two main motivations: (i) to provide the asynchronous circuit designers with a powerful execution/simulation framework mixing high-level CSP descriptions, HDL programs and gate level descriptions, (ii) to give to synchronous designers familiar with existing HDL-based top-down design flows, the opportunity to include clockless circuits in their designs. An extension of the CHP language proposed by A.J. Martin (1990) is presented and its simulation-oriented features are discussed. The "CHP/sub 2/VHDL" translator and its software environment are then described. Finally, a significant design experiment is considered to illustrate the efficiency of the design framework.
提出了一种允许混合异步和同步电路风格的开放式设计框架。它基于一种名为“CHP/sub 2/VHDL”的工具的开发,该工具可以自动将类似csp的规范(通信顺序过程)转换为VHDL程序。这项工作有两个主要动机:(i)为异步电路设计人员提供一个强大的执行/仿真框架,混合高级CSP描述,HDL程序和门级描述;(ii)为熟悉现有基于HDL的自顶向下设计流程的同步设计人员提供在其设计中包含无时钟电路的机会。提出了A.J. Martin(1990)提出的CHP语言的扩展,并讨论了其面向仿真的特性。然后介绍了“CHP/ sub2 /VHDL”转换器及其软件环境。最后,通过一个重要的设计实验来说明设计框架的有效性。
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引用次数: 34
Memory faults in asynchronous microprocessors 异步微处理器中的内存故障
D. Lloyd, J. Garside, D. A. Gilbert
Although a large number of asynchronous microprocessors have now been designed, relatively few have attempted to handle memory faults. Memory faults create problems for the design of any pipelined system which are exacerbated by the non-deterministic nature of an asynchronous processor. This paper describes these problems as encountered in the design of asynchronous ARM processors and discusses their specific solutions in the AMULET3 processor. Different mechanisms were used, as expedient, to maintain coherency for the various state-holding elements within the processor; these include register renaming and history buffering in addition to resource locking.
虽然现在已经设计了大量的异步微处理器,但相对而言,很少有人尝试处理内存故障。内存故障会给任何流水线系统的设计带来问题,而异步处理器的不确定性又加剧了这种问题。本文描述了异步ARM处理器设计中遇到的这些问题,并讨论了在AMULET3处理器中解决这些问题的具体方法。为了方便起见,使用了不同的机制来保持处理器内各种状态保持元素的一致性;除了资源锁定之外,还包括寄存器重命名和历史缓冲。
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引用次数: 0
A timing verifier and timing profiler for asynchronous circuits 异步电路的定时验证器和定时分析器
Per Arne Karlsen, P. T. Røine
A system for timing verification and timing profiling of asynchronous circuits is presented. A hierarchical netlist is simulated with an ordinary simulator such as HSPICE. Signal transition information is extracted from the simulation results. The system uses this information and the netlist to compare the circuit to generalized signal transition graph specifications by simulating the flow of tokens in the graphs. If a signal makes a transition that is not allowed by the specification, a timing error has occurred. The flow of tokens in the graph is also used to produce timing statistics for the circuit. Based on these statistics, timing optimization can be done in an iterative design process.
提出了一种异步电路时序验证和时序分析系统。用HSPICE等普通模拟器对分层网表进行了仿真。从仿真结果中提取信号过渡信息。系统利用这些信息和网络表,通过模拟图中符号的流动,将电路与广义信号转换图规范进行比较。如果信号进行了规范不允许的转换,则发生了时序错误。图中的令牌流也用于产生电路的定时统计。基于这些统计数据,可以在迭代设计过程中进行时间优化。
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引用次数: 5
Symbolic time separation of events 事件的象征性时间分离
T. Amon, H. Hulgaard
We extend the TSE timing analysis algorithm into the symbolic domain; that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are (1) an iterative algorithm which continuously narrows down the domain of interest and (2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know.
将TSE时序分析算法扩展到符号域;也就是说,我们允许使用符号变量来指定模型的未知参数(本质上是未知延迟)和验证算法,这些算法不仅能够识别失败或成功,而且还能够识别这些符号变量的约束,这些约束将确保成功验证。两个主要贡献是:(1)不断缩小感兴趣领域的迭代算法和(2)减少包含给定领域定义的最小化和最大化的符号表达式的表示的实用方法。我们报告了几个异步电路的实验结果,以证明符号分析是可行的,并且提供的输出是设计师(或可能是合成工具)经常想知道的。
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引用次数: 6
AMULET3 revealed AMULET3透露
J. Garside, S. Furber, Shiaw-Horng Chung
AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a recorder buffer to handle data forwarding and memory faults.
AMULET3是曼彻斯特大学设计的ARM架构的第三个完全异步实现。它实现了最新版本的ARM架构(v4T),包括Thumb指令集。其前身的重大架构变化有助于在不牺牲异步设计优势的情况下实现更高的性能,并纳入了一些新的节能特性。本文概述了AMULET3微处理器核心,突出了该设计与之前设计的不同之处。最值得注意的变化是使用哈佛架构来增加内存带宽,并包含一个记录器缓冲区来处理数据转发和内存故障。
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引用次数: 47
Verification of delayed-reset domino circuits using ATACS 用ATACS验证延迟复位多米诺电路
W. Belluomini, C. Myers, H. P. Hofstee
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self-resetting style since internally, a block of self-resetting or delayed-reset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The state-space explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance.
本文讨论了时序分析工具ATACS在IBM奥斯汀研究实验室设计的高性能、自复位和延迟复位多米诺电路中的应用。该工具最初是为处理异步电路而开发的,它非常适合自重置样式,因为在内部,自重置或延迟重置的domino逻辑块是异步的。电路用定时事件/级别结构表示。这些结构非常直接地对应于门电平电路,使得从晶体管原理图到TEL结构的转换非常简单。采用一种基于部分有序集(POSETs)的算法来缓解状态空间爆炸问题。来自IBM最近发布的guTS(千兆赫单元测试站点)处理器的许多电路的结果表明,可以使用ATACS使用保留电路有趣的时序特性的抽象级别来验证显着尺寸的模块。精确的电路电平验证允许设计人员在设计中包含更少的余量,这可以提高性能。
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引用次数: 20
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Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
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