A strategy for long data retention time of 512 Mb DRAM with 0.12 /spl mu/m design rule

Abstract

Data retention time has been investigated for mass-produced 512 Mb DRAMs with 0.12 /spl mu/m design rules. Cell junction leakage components were analyzed for the first time using a test structure. It was found that process-induced trap density and electric field at the storage node (SN) junction should be reduced to control leakage current and thus data retention time. Moreover, we propose a novel cell transistor using localized channel and field implantation (LOCFI) which greatly suppresses the ion implantation damage and reduces the electric field at the same time. Finally, data retention time has been improved by 3/spl sim/4 times due to the LOCFI cell transistor with optimized process conditions.