{"title":"A CMOS-Compatible WORM Memory for Low-Cost Non-Volatile Memory Applications","authors":"R. Barsatan, T. Y. Man, M. Chan","doi":"10.1109/EDSSC.2005.1635276","DOIUrl":null,"url":null,"abstract":"A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at milliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635276","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A Write-Once-Read-Many (WORM) memory using a CMOS-compatible Antifuse (AF) element for low-cost nonvolatile memory is presented. The AF device is formed on an NMOS with PLDD implants (MOS-channel AF) to enhance hot-carrier effects. The AF is programmed by applying a high voltage across the channel until breakdown such that it becomes resistor. The devices were fabricated in standard TSMC 0.18μm process without any process modification. The channel breakdown was observed between 4.5V to 5V. The programmed resistance is in the kΩ range at milliampere range of programming current. A 128-bit WORM architecture is presented based on an IO-select transistor and the AF memory cell. The architecture was designed and simulated in Cadence to verify the functionality of the device when formed in an array.
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