Pub Date : 2007-04-01DOI: 10.1093/ietele/e90-c.4.735
T. Kawahara
Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted SOI are presented. Then, DRAM approach with a novel twin- cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.
{"title":"Low-voltage embedded RAMs in the nanometer era","authors":"T. Kawahara","doi":"10.1093/ietele/e90-c.4.735","DOIUrl":"https://doi.org/10.1093/ietele/e90-c.4.735","url":null,"abstract":"Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted SOI are presented. Then, DRAM approach with a novel twin- cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129278053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635311
Jang-Woo Ryu, E. Kang, H. Park, M. Sung
In this Paper, we present a design of source driver driving a current driven AMOLED Panel. Generally, a current driven AMOLED pixel has a long programming time in low current level. But, the proposed source driver reduces a programming time with employing a voltage DAC for pre-charging. It will make possible to use the large scale display panel on mobile applications even stationary applications.
{"title":"A Design of AM-OLED Source Driver with reduced Programming Time for a Large Scale Display Panel","authors":"Jang-Woo Ryu, E. Kang, H. Park, M. Sung","doi":"10.1109/EDSSC.2005.1635311","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635311","url":null,"abstract":"In this Paper, we present a design of source driver driving a current driven AMOLED Panel. Generally, a current driven AMOLED pixel has a long programming time in low current level. But, the proposed source driver reduces a programming time with employing a voltage DAC for pre-charging. It will make possible to use the large scale display panel on mobile applications even stationary applications.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115590500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635227
H. Shi, J.H. Liu, G.Y. Zhang, H. Liao, R. Huang, Y.Y. Wang
When the tuning range of the RF LC VCO gets very large, the VCO start up condition, VCO oscillation swing and phase noise performance will vary obviously. These issues result from the fact that the equivalent parallel resistance of the LC tank varies a lot due to very large tuning range. In this paper, we propose a variable negative Gm technique to solve these problems. From simulation results, it is found that by using this technique the VCO start up condition at different frequency bands can be independently met. The variation of the VCO oscillation swing can be effectively reduced. The phase noise fluctuations between different bands can be decreased close to the intrinsic level.
{"title":"Variable Negative Gm Technique for RF LC VCO with Very Large Tuning Range","authors":"H. Shi, J.H. Liu, G.Y. Zhang, H. Liao, R. Huang, Y.Y. Wang","doi":"10.1109/EDSSC.2005.1635227","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635227","url":null,"abstract":"When the tuning range of the RF LC VCO gets very large, the VCO start up condition, VCO oscillation swing and phase noise performance will vary obviously. These issues result from the fact that the equivalent parallel resistance of the LC tank varies a lot due to very large tuning range. In this paper, we propose a variable negative Gm technique to solve these problems. From simulation results, it is found that by using this technique the VCO start up condition at different frequency bands can be independently met. The variation of the VCO oscillation swing can be effectively reduced. The phase noise fluctuations between different bands can be decreased close to the intrinsic level.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116789188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635223
Z. Deng, A. Niknejad
We present a new voltage-controlled oscillator structure featuring dual-mode outputs which are mutually locked to octave bands, while consuming only one current branch. The characteristics of coupled LC tanks are analyzed and a structure for realization of a low current dual mode oscillator is presented. A prototype has been fabricated and measured to demonstrate the feasibility of the idea.
{"title":"Dual-Mode Voltage-Controlled Oscillator with Injection Lock","authors":"Z. Deng, A. Niknejad","doi":"10.1109/EDSSC.2005.1635223","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635223","url":null,"abstract":"We present a new voltage-controlled oscillator structure featuring dual-mode outputs which are mutually locked to octave bands, while consuming only one current branch. The characteristics of coupled LC tanks are analyzed and a structure for realization of a low current dual mode oscillator is presented. A prototype has been fabricated and measured to demonstrate the feasibility of the idea.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"51 7-8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120940476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635352
Meng-Lieh Sheu, Chih-Kuan Lai, W. Hsu, Hong-Ming Yang
In this paper, a novel capacitive sensing scheme for fingerprint acquisition is presented. Based on capacitive fingerprint sensing, a novel capacitive sensor structure and readout circuit are proposed to grab the induced capacitance by the finger directly touched to the sensor plate. A test array of 32x32 capacitive fingerprint sensors is implemented in a standard CMOS 0.35-μm technology. Including the sensor array and peripheral digital control circuit, the chip area is 2550x1890μm2.
{"title":"A Novel Capacitive Sensing Scheme for Fingerprint Acquisition","authors":"Meng-Lieh Sheu, Chih-Kuan Lai, W. Hsu, Hong-Ming Yang","doi":"10.1109/EDSSC.2005.1635352","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635352","url":null,"abstract":"In this paper, a novel capacitive sensing scheme for fingerprint acquisition is presented. Based on capacitive fingerprint sensing, a novel capacitive sensor structure and readout circuit are proposed to grab the induced capacitance by the finger directly touched to the sensor plate. A test array of 32x32 capacitive fingerprint sensors is implemented in a standard CMOS 0.35-μm technology. Including the sensor array and peripheral digital control circuit, the chip area is 2550x1890μm2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124956024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635323
S. Pisitchalermpong, T. Pukkalanun, W. Tangsrirat, W. Surakampontorn
In this paper, multiple-output multifunctional biquadratic filters using current differencing buffered amplifiers (CDBAs) as active elements are presented. The proposed circuit topologies are mainly composed of the CDBA-based cross-coupled feedback configuration and the voltage substractor. By an appropriate choice of virtually grounded passive components, the configurations can simultaneously realize lowpass, highpass, bandpass, bandstop and allpass voltage transfer functions, all at low resistance outputs. The natural angular frequency and the quality factor can orthogonal controllable. PSPICE simulation results demonstrating the feasibility of the technique are also included.
{"title":"Current Differencing Buffered Amplifier Based Multiple-output Biquadratic Filters","authors":"S. Pisitchalermpong, T. Pukkalanun, W. Tangsrirat, W. Surakampontorn","doi":"10.1109/EDSSC.2005.1635323","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635323","url":null,"abstract":"In this paper, multiple-output multifunctional biquadratic filters using current differencing buffered amplifiers (CDBAs) as active elements are presented. The proposed circuit topologies are mainly composed of the CDBA-based cross-coupled feedback configuration and the voltage substractor. By an appropriate choice of virtually grounded passive components, the configurations can simultaneously realize lowpass, highpass, bandpass, bandstop and allpass voltage transfer functions, all at low resistance outputs. The natural angular frequency and the quality factor can orthogonal controllable. PSPICE simulation results demonstrating the feasibility of the technique are also included.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126012376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635378
Sang Won Park, S. Hwang, Jang-Woo Ryu, S. Hong, M. Sung
Infrared bolometer sensor's variation is detected by voltage drop between a reference resistor and a bolometer resistor in this architecture. One of the serious problems in this architecture is that these resistors value has a process variation. So common-mode level could be different from expectation value in room temperature. Different common-mode level could lead to wrong output at the end of readout circuit. We suggest useful method to solve this problem. Difference correction using capacitor has reduced CM level difference to 88.5 % for I MΩ bolometer and reference resistor's 10 % variation.
{"title":"Bias Offset Correction Technique For Uncooled Infrared Bolometer Sensor Readout IC","authors":"Sang Won Park, S. Hwang, Jang-Woo Ryu, S. Hong, M. Sung","doi":"10.1109/EDSSC.2005.1635378","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635378","url":null,"abstract":"Infrared bolometer sensor's variation is detected by voltage drop between a reference resistor and a bolometer resistor in this architecture. One of the serious problems in this architecture is that these resistors value has a process variation. So common-mode level could be different from expectation value in room temperature. Different common-mode level could lead to wrong output at the end of readout circuit. We suggest useful method to solve this problem. Difference correction using capacitor has reduced CM level difference to 88.5 % for I MΩ bolometer and reference resistor's 10 % variation.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115216074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635297
Y. Kuo, R. Weng, Chuanyu Liu
A fast locking phase-locked loops (PLL) with a phase error detector (PED) circuit is presented. The PED circuit is composed of a dual-slop phase frequency detector and a charge-pump characteristic. The proposed architecture can efficiently reduce both the power dissipation and the acquisition time of the PLL while the loop stability remains unchanged. The proposed PLL is designed in a standard CMOS 0.35μm technology through a 3.3V power supply. The simulation results show that the settling time of the proposed PLL is below 150ns. There is over 50% reduction of the locked time in comparison with the conventional PLLs. The power consumption is 18.5mW at 2.4GHz.
{"title":"A Fast Locking PLL With Phase Error Detector","authors":"Y. Kuo, R. Weng, Chuanyu Liu","doi":"10.1109/EDSSC.2005.1635297","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635297","url":null,"abstract":"A fast locking phase-locked loops (PLL) with a phase error detector (PED) circuit is presented. The PED circuit is composed of a dual-slop phase frequency detector and a charge-pump characteristic. The proposed architecture can efficiently reduce both the power dissipation and the acquisition time of the PLL while the loop stability remains unchanged. The proposed PLL is designed in a standard CMOS 0.35μm technology through a 3.3V power supply. The simulation results show that the settling time of the proposed PLL is below 150ns. There is over 50% reduction of the locked time in comparison with the conventional PLLs. The power consumption is 18.5mW at 2.4GHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114173396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635236
K. Xue, J. An, L. Wang, X.J. Yu, H. Ho, J.B. Xu
By exploiting the powerful local ability of scanning tunneling microscopy (STM), we studied the ultrathin SiO2degradation and soft-breakdown (SBD) by both DC and dynamic electrical stressing (DES). The results show that the SBD is a local event and characterized by bright spot generation which represents high conductive pathways formed in the oxide. The degradation is not a reversible process and has no observable relaxation effects. By comparing the SBD generation under DC and DES stress, it is found that the SBD density versus stress time can be described by the Weibull statistics. Both the SBD generation rate and final SBD density are lower for DES stressing than for DC stressing, suggesting that a critical energy exists for SBD to be generated.
{"title":"Local Study of DC and Dynamic Electrical Stress Induced Ultrathin Gate Oxide Soft-Breakdown by Scanning Tunneling Microscopy","authors":"K. Xue, J. An, L. Wang, X.J. Yu, H. Ho, J.B. Xu","doi":"10.1109/EDSSC.2005.1635236","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635236","url":null,"abstract":"By exploiting the powerful local ability of scanning tunneling microscopy (STM), we studied the ultrathin SiO2degradation and soft-breakdown (SBD) by both DC and dynamic electrical stressing (DES). The results show that the SBD is a local event and characterized by bright spot generation which represents high conductive pathways formed in the oxide. The degradation is not a reversible process and has no observable relaxation effects. By comparing the SBD generation under DC and DES stress, it is found that the SBD density versus stress time can be described by the Weibull statistics. Both the SBD generation rate and final SBD density are lower for DES stressing than for DC stressing, suggesting that a critical energy exists for SBD to be generated.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129480405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635192
P. Kinget, S. Chatterjee, Y. Tsividis
This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 μm CMOS technology.
{"title":"Ultra-Low Voltage Analog Design Techniques for Nanoscale CMOS Technologies","authors":"P. Kinget, S. Chatterjee, Y. Tsividis","doi":"10.1109/EDSSC.2005.1635192","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635192","url":null,"abstract":"This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 μm CMOS technology.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128465665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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