A low jitter, fast recoverable, fully analog DLL using tracking ADC for high speed and low stand-by power DDR I/O interface

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221228

Se Jun Kim, Sang-Hoon Hong, J. Wee, Jin-Hong Ahn, J. Chung

引用次数: 7

Abstract

For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16 /spl mu/m DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100 MHz/spl sim/520 MHz wide lock-range and a 65 psec peak-to-peak jitter and 0.064 psec/mv supply sensitivity at 2.3 v supply voltage consuming 1.1 mA of stand-by current.

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一个低抖动，快速恢复，全模拟DLL使用跟踪ADC为高速和低待机功率DDR I/O接口

针对高带宽和低待机功耗的DDR(双数据速率)I/O接口，设计并实现了一种新的全模拟DLL(延迟锁相环)，其速度为0.16 /spl mu/m DRAM。利用跟踪ADC(模数转换器)，模拟DLL的大待机电流被抑制，而不会丢失锁定信息，也不会影响抖动性能。采用多相时钟和相位混频的两步占空校正方案，对系统时钟固有的占空误差具有更高的校正精度和速度，尤其适用于较大的占空误差。所提出的DLL具有100 MHz/spl sim/520 MHz宽锁程和65 psec峰间抖动，在2.3 v电源电压消耗1.1 mA待机电流时具有0.064 psec/mv的电源灵敏度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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